SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This mode is used if the TIMER_TSICR[2] POSTED bit is set to 0. It uses a nonposted write scheme to update any internal register. Therefore, the write transaction is not acknowledged on the configuration interface until the effective write operation occurs after the resynchronization in the timer functional clock domain. The drawback is that the interconnect and the device that requested the write transaction are stalled during this period.
The same full resynchronization scheme is used for a read transaction, and the same stall period applies. A register read following a write to the same register is always coherent.
This mode is functional regardless of the ratio between the configuration interface frequency and the timer clock frequency.