SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-1757 lists the memory-mapped registers for the MCU_CPSW0_NUSS SS registers. All register offset addresses not listed in Table 12-1757 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_CPSW0_NUSS_SS | 4600 0000h |
Offset | Acronym | Register Name | MCU_CPSW0_NUSS_SS Physical Address |
---|---|---|---|
0h | CPSW_SS_CPSW_NUSS_IDVER_REG | ID Version Register | 4600 0000h |
4h | CPSW_SS_SYNCE_COUNT_REG | SyncE Count Register | 4600 0004h |
8h | CPSW_SS_SYNCE_MUX_REG | SyncE Mux Select Register | 4600 0008h |
Ch | CPSW_SS_CONTROL_REG | Subsystem Control Register | 4600 000Ch |
30h | CPSW_SS_RGMII_STATUS_REG | RGMII Port 1 Register | 4600 0018h |
1Ch | CPSW_SS_SUBSSYSTEM_STATUS_REG | Subsystem Status Register | 4600 001Ch |
CPSW_SS_CPSW_NUSS_IDVER_REG is shown in Figure 12-520 and described in Table 12-962.
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CPSW_NUSS ID Version Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_SS | 4600 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IDENT | |||||||||||||||
R-6BA0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL_VER | MAJOR_VER | MINOR_VER | |||||||||||||
R-0h | R-1h | R-1h | |||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | IDENT | R | 6BA0h | Identification value |
15-11 | RTL_VER | R | 0h | RTL version value |
10-8 | MAJOR_VER | R | 1h | Major version value |
7-0 | MINOR_VER | R | 1h | Minor version value |
CPSW_SS_SYNCE_COUNT_REG is shown in Figure 12-521 and described in Table 12-964.
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CPSW_NUSS SYNCE Count Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_SS | 4600 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYNCE_CNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SYNCE_CNT | R/W | 0h | Sync E Count Value |
CPSW_SS_SYNCE_MUX_REG is shown in Figure 12-522 and described in Table 12-966.
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CPSW_NUSS Synce Mux Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_SS | 4600 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYNCE_SEL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | X | |
5-0 | SYNCE_SEL | R/W | 0h | Sync E Select Value |
CPSW_SS_CONTROL_REG is shown in Figure 12-523 and described in Table 12-968.
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CPSW_NUSS Control Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_SS | 4600 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EEE_PHY_ONLY | EEE_EN | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | EEE_PHY_ONLY | R/W | 0h | Energy Efficient Enable Phy Only Mode: 0=The low power indicate state includes gating off the CPPI_GCLK to the CPSW, 1=The low power indicate state does not gate the clock to the CPSW |
0 | EEE_EN | R/W | 0h | Energy Efficient Ethernet Enable: 0=EEE is disabled, 1=EEE is enabled |
CPSW_SS_RGMII_STATUS_REG is shown in Figure 12-524 and described in Table 12-970.
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CPSW_NUSS RGMII Status Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_SS | 4600 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FULLDUPLEX | SPEED | LINK | ||||
R-X | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | X | |
3 | FULLDUPLEX | R | 0h | Rgmii full dulex: 0=Half-duplex, 1=Full-duplex |
2-1 | SPEED | R | 0h | Rgmii speed: 00=10Mbps, 01=100Mbps, 10=1000Mbps, 11=reserved |
0 | LINK | R | 0h | Rgmii link indicator: 0=Link is down, 1=Link is up |
CPSW_SS_SUBSSYSTEM_STATUS_REG is shown in Figure 12-525 and described in Table 12-972.
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CPSW_NUSS Status Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_SS | 4600 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EEE_CLKSTOP_ACK | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | |
0 | EEE_CLKSTOP_ACK | R | 0h | Energy Efficient Ethernet clockstop acknowledge from CPSW |