SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The COMPUTE_CLUSTER0 encompasses the Arm® Cortex®-A72 subsystem, Generic Interrupt Controller (GIC), Multicore Shared Memory Controller (MSMC), AXI to VBUSM.C bridge, ECC aggregators and debug components. Figure 6-1 shows an overview of the COMPUTE_CLUSTER0 and its surrounding modules.