SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 3-49 through Table 3-56 list the memory-mapped QoS registers for the system interconnect masters. All register offset addresses not listed in these tables should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address | CBASS_MAP_i Fields Availability |
---|---|---|
MCU_R5FSS0_CORE0_MEM_RD | 45D1 0000h | ATYPE, VIRTID, EPRIORITY, ORDERID, QOS |
MCU_R5FSS0_CORE0_MEM_WR | 45D1 0400h | ATYPE, VIRTID, EPRIORITY, ORDERID, QOS |
MCU_R5FSS0_CORE0_PER0 | 45D1 0800h | EPRIORITY, ORDERID, QOS |
MCU_R5FSS0_CORE1_MEM_RD | 45D1 1000h | ATYPE, VIRTID, EPRIORITY, ORDERID, QOS |
MCU_R5FSS0_CORE1_MEM_WR | 45D1 1400h | ATYPE, VIRTID, EPRIORITY, ORDERID, QOS |
MCU_R5FSS0_CORE1_PER0 | 45D1 1800h | EPRIORITY, ORDERID, QOS |
R5FSS0_CORE0_PER1_RD | 45D7 8000h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
R5FSS0_CORE0_PER1_WR | 45D7 8400h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
R5FSS0_CORE1_PER1_RD | 45D7 8800h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
R5FSS0_CORE1_PER1_WR | 45D7 8C00h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
MMCSD0_RD | 45D8 2000h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
MMCSD0_WR | 45D8 2400h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
MMCSD1_WR | 45D8 2800h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
MMCSD1_RD | 45D8 2C00h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
GIC0_RD | 45D8 6000h | EPRIORITY, ASEL, ORDERID, QOS |
GIC0_WR | 45D8 6400h | EPRIORITY, ASEL, ORDERID, QOS |
USB3SS0_RD | 45D9 8C00h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
USB3SS0_WR | 45D9 9000h | ATYPE, VIRTID, EPRIORITY, ASEL, ORDERID, QOS |
PCIE1_RD | 45D9 9400h | EPRIORITY, ASEL, ORDERID, QOS |
PCIE1_WR | 45D9 9C00h | EPRIORITY, ASEL, ORDERID, QOS |
DEBUGSS0_RD | 45DA 0000h | EPRIORITY, ASEL, ORDERID, QOS |
DEBUGSS0_WR | 45DA 0400h | EPRIORITY, ASEL, ORDERID, QOS |
Offset | Acronym | Register Name | MCU_R5FSS0_CORE0_MEM_RD Physical Address | MCU_R5FSS0_CORE0_MEM_WR Physical Address | MCU_R5FSS0_CORE0_PER0 Physical Address |
---|---|---|---|---|---|
0h + j*8 | CBASS_GRP_MAP1_j(1) | Group j Map Register 1 | NA | NA | NA |
4h + j*8 | CBASS_GRP_MAP2_j(1) | Group j Map Register 2 | NA | NA | NA |
100h + i*4 | CBASS_MAP_i(1) | Map Register i | 45D1 0100h + i*4 | 45D1 0500h + i*4 | 45D1 0900h + i*4 |
Offset | Acronym | Register Name | MCU_R5FSS0_CORE1_MEM_RD Physical Address | MCU_R5FSS0_CORE1_MEM_WR Physical Address | MCU_R5FSS0_CORE1_PER0 Physical Address |
---|---|---|---|---|---|
0h + j*8 | CBASS_GRP_MAP1_j(1) | Group j Map Register 1 | NA | NA | NA |
4h + j*8 | CBASS_GRP_MAP2_j(1) | Group j Map Register 2 | NA | NA | NA |
100h + i*4 | CBASS_MAP_i(1) | Map Register i | 45D1 1100h + i*4 | 45D1 1500h + i*4 | 45D1 1900h + i*4 |
Offset | Acronym | Register Name | R5FSS0_CORE0_PER1_RD Physical Address | R5FSS0_CORE0_PER1_WR Physical Address | R5FSS0_CORE1_PER1_RD Physical Address |
---|---|---|---|---|---|
0h + j*8 | CBASS_GRP_MAP1_j(1) | Group j Map Register 1 | NA | NA | NA |
4h + j*8 | CBASS_GRP_MAP2_j(1) | Group j Map Register 2 | NA | NA | NA |
100h + i*4 | CBASS_MAP_i(1) | Map Register i | 45D7 8100h + i*4 | 45D7 8500h + i*4 | 45D7 8900h + i*4 |
Offset | Acronym | Register Name | R5FSS0_CORE1_PER1_WR Physical Address | MMCSD0_RD Physical Address | MMCSD0_WR Physical Address |
---|---|---|---|---|---|
0h + j*8 | CBASS_GRP_MAP1_j(1) | Group j Map Register 1 | NA | 45D8 2000h + j*8 | 45D8 2400h + j*8 |
4h + j*8 | CBASS_GRP_MAP2_j(1) | Group j Map Register 2 | NA | 45D8 2004h + j*8 | 45D8 2404h + j*8 |
100h + i*4 | CBASS_MAP_i(1) | Map Register i | 45D7 8D00h + i*4 | 45D8 2100h + i*4 | 45D8 2500h + i*4 |
Offset | Acronym | Register Name | MMCSD1_WR Physical Address | MMCSD1_RD Physical Address | GIC0_RD Physical Address |
---|---|---|---|---|---|
0h + j*8 | CBASS_GRP_MAP1_j(1) | Group j Map Register 1 | 45D8 2800h + j*8 | 45D8 2C00h + j*8 | 45D8 6000h + j*8 |
4h + j*8 | CBASS_GRP_MAP2_j(1) | Group j Map Register 2 | 45D8 2804h + j*8 | 45D8 2C04h + j*8 | 45D8 6004h + j*8 |
100h + i*4 | CBASS_MAP_i(1) | Map Register i | 45D8 2900h + i*4 | 45D8 2D00h + i*4 | 45D8 6100h + i*4 |
Offset | Acronym | Register Name | GIC0_WR Physical Address | USB3SS0_RD Physical Address | USB3SS0_WR Physical Address |
---|---|---|---|---|---|
0h + j*8 | CBASS_GRP_MAP1_j(1) | Group j Map Register 1 | 45D8 6400h + j*8 | NA | NA |
4h + j*8 | CBASS_GRP_MAP2_j(1) | Group j Map Register 2 | 45D8 6404h + j*8 | NA | NA |
100h + i*4 | CBASS_MAP_i(1) | Map Register i | 45D8 6500h + i*4 | 45D9 8D00h + i*4 | 45D9 9100h + i*4 |
Offset | Acronym | Register Name | PCIE1_RD Physical Address | PCIE1_WR Physical Address | DEBUGSS0_RD Physical Address |
---|---|---|---|---|---|
0h + j*8 | CBASS_GRP_MAP1_j(1) | Group j Map Register 1 | NA | NA | NA |
4h + j*8 | CBASS_GRP_MAP2_j(1) | Group j Map Register 2 | NA | NA | NA |
100h + i*4 | CBASS_MAP_i(1) | Map Register i | 45D9 9500h + i*4 | 45D9 9D00h + i*4 | 45DA 0100h + i*4 |
Offset | Acronym | Register Name | DEBUGSS0_WR Physical Address |
---|---|---|---|
0h + j*8 | CBASS_GRP_MAP1_j(1) | Group j Map Register 1 | NA |
4h + j*8 | CBASS_GRP_MAP2_j(1) | Group j Map Register 2 | NA |
100h + i*4 | CBASS_MAP_i(1) | Map Register i | 45DA 0500h + i*4 |
CBASS_GRP_MAP1_j is shown in Figure 3-11 and described in Table 3-58.
Return to Summary Table.
The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7.
Instance | Base Address |
---|---|
See Table 3-49 through Table 3-56 | See Table 3-49 through Table 3-56 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ORDERID7 | ORDERID6 | ORDERID5 | ORDERID4 | ||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ORDERID3 | ORDERID2 | ORDERID1 | ORDERID0 | ||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | ORDERID7 | R/W | 0h | Final order ID value for initial order ID value of 7. |
27-24 | ORDERID6 | R/W | 0h | Final order ID value for initial order ID value of 6. |
23-20 | ORDERID5 | R/W | 0h | Final order ID value for initial order ID value of 5. |
19-16 | ORDERID4 | R/W | 0h | Final order ID value for initial order ID value of 4. |
15-12 | ORDERID3 | R/W | 0h | Final order ID value for initial order ID value of 3. |
11-8 | ORDERID2 | R/W | 0h | Final order ID value for initial order ID value of 2. |
7-4 | ORDERID1 | R/W | 0h | Final order ID value for initial order ID value of 1. |
3-0 | ORDERID0 | R/W | 0h | Final order ID value for initial order ID value of 0. |
CBASS_GRP_MAP2_j is shown in Figure 3-12 and described in Table 3-60.
Return to Summary Table.
The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15.
Instance | Base Address |
---|---|
See Table 3-49 through Table 3-56 | See Table 3-49 through Table 3-56 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ORDERID15 | ORDERID14 | ORDERID13 | ORDERID12 | ||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ORDERID11 | ORDERID10 | ORDERID9 | ORDERID8 | ||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | ORDERID15 | R/W | 0h | Final order ID value for initial order ID value of 15. |
27-24 | ORDERID14 | R/W | 0h | Final order ID value for initial order ID value of 14. |
23-20 | ORDERID13 | R/W | 0h | Final order ID value for initial order ID value of 13. |
19-16 | ORDERID12 | R/W | 0h | Final order ID value for initial order ID value of 12. |
15-12 | ORDERID11 | R/W | 0h | Final order ID value for initial order ID value of 11. |
11-8 | ORDERID10 | R/W | 0h | Final order ID value for initial order ID value of 10. |
7-4 | ORDERID9 | R/W | 0h | Final order ID value for initial order ID value of 9. |
3-0 | ORDERID8 | R/W | 0h | Final order ID value for initial order ID value of 8. |
CBASS_MAP_i is shown in Figure 3-13 and described in Table 3-62.
Return to Summary Table.
The Map Register defines the fields for the master per channel.
Instance | Base Address |
---|---|
See Table 3-49 through Table 3-56 | See Table 3-49 through Table 3-56 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | ATYPE | VIRTID | |||||
R/W-X | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
VIRTID | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | EPRIORITY | ASEL | |||||
R/W-X | R/W-7h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ORDERID | RESERVED | QOS | |||||
R/W-0h | R/W-X | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | X | |
29-28 | ATYPE(1) | R/W | 0h | atype signal for channel "i". 0h = Not translated physical 1h = Intermediate 2h = Virtual (Not supported on this device) 3h = Physical with coherence |
27-16 | VIRTID(1) | R/W | 0h | virtid signal for channel "i". |
15 | RESERVED | R/W | X | |
14-12 | EPRIORITY(1) | R/W | 7h | epriority signal for channel "i". |
11-8 | ASEL(1) | R/W | 0h | asel signal for channel "i". 0h = SoC address 1h-Fh = Peripheral address |
7-4 | ORDERID(1) | R/W | 0h | orderid signal for channel "i". |
3 | RESERVED | R/W | X | |
2-0 | QOS(1) | R/W | 0h | qos signal for channel "i". |