SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-542 shows the MODSS Interrupt Aggregators 0 and 1, and UDMASS Interrupt Aggregator 0 parameters set during design time. 4 local (LEVI) interrupts are from the MCRC0 module. 48 LEVI interrupts are from the MAILBOX0 module. See INTR_AGGR Integration.
Module Instance | Parameters | ||||
VINTR(1) | SEVI(2) | GEVI(3) | LEVI(4) | MEVI(5) | |
NAVSS0_INTR_AGGR0 | 64 | 1024 | 0 | 0 | 0 |
NAVSS0_INTR_AGGR1 | 64 | 1024 | 0 | 0 | 0 |
NAVSS0_UDMASS_INTR_AGGR0 | 256 | 4608 | 512 | 84 | 512 |
MCU_NAVSS0_UDMASS_INTR_AGGR0 | 256 | 1536 | 256 | 12 | 128 |