SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
For synchronization to other modules or events EPWMs are provided with synchronization signals. In the device, these signals are connected in a daisy-chain fashion as shown in Figure 12-2604. The EPWM0 input synchronization signal is terminated at a device pad (EHRPWM0_SYNCI signal), such that device external sync events can be directly applied only to the EPWM0 submodule. The EPWM3 through EPWM5 modules can be synchronized either from a separate external signal on the EHRPWM3_SYNCI pin or from EPWM2 output synchronization signal. The EPWM3 input synchronization signal is selected using the corresponding SYNCIN_SEL bit field of the CTRLMMR_EPWM3_CTRL register in the CTRL_MMR0 module. A synchronization output is available from the EPWM0 on the EHRPWM0_SYNCO output pin and from EPWM3 on the EHRPWM3_SYNCO pin.
The EPWM0 EPWM0SYNCI signal (device EHRPWM0_SYNCI input signal) triggers the event of the EPWM0 Phase Register being loaded into the Counter register (TBPHS -> TBCNT). This event is synchronous to the EPWM0 time-base clock (TBCLK).
The EPWM0 EPWM0SYNCO (device EHRPWM0_SYNCO output signal) is implicitly synchronous to the time-base clock, as this signal has a programmable source of event (in the EPWM_TBCTL[5-4] SYNCOSEL bit field) triggered synchronously to the EPWM0 TBCLK.
The EPWM0SYNCI and EPWM3SYNCI inputs of EPWM0 and EPWM3 modules can be connected to one of several external event sources. These sources must be synchronized to the EPWM clock domain to prevent propagation of metastable state. A synchronizer (signified with (1) Sync of the figure above) has been implemented in the path to resolve this potential issue. However, the synchronizer inserts a delay which may need to be accounted in some applications of the EPWM module.