SPRUIZ2 july   2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2838x and F28P65x
    1. 1.1 F2838x and F28P65x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 176-Pin PTP Package
    2. 2.2 Use of Existing 176-Pin F2838x PCB Design
      1.      9
      2. 2.2.1 JTAG TRSTn No-Connect
      3. 2.2.2 GPIO Input Buffer Control Register
      4. 2.2.3 176-Pin GPIO Pin/Multiplex and ADCD Considerations
        1. 2.2.3.1 176-Pin PTP Pins With Different GPIO Assignment
        2. 2.2.3.2 ADCD Channel Migration
    3. 2.3 176-Pin PTP New PCB Design
    4. 2.4 337-BGA ZWT Application to 256-BGA ZEJ or 169-BGA NMR
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P65x
      1. 3.1.1  Lock-step Compare Module (LCM)
      2. 3.1.2  Expanded Analog Channels
      3. 3.1.3  Firmware Update (FWU)
      4. 3.1.4  Flexible GPIO and Digital Input Pins
      5. 3.1.5  New ADC Features
      6. 3.1.6  New EPWM Features
      7. 3.1.7  New CMPSS Features
      8. 3.1.8  ADC Hardware Redundancy Safety Checker
      9. 3.1.9  Flexible Memory Sharing between CPU Subsystems
      10. 3.1.10 Increased RAM Program Memory on CLA
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PIE Channel Mapping
        1. 3.5.1.1 F2838x vs F28P65x PIE Channel Mapping Comparison
      2. 3.5.2 Bootrom
      3. 3.5.3 CLB and Motor Control Libraries
      4. 3.5.4 ERAD
      5. 3.5.5 AGPIO Filter
    6. 3.6 Power Management
      1. 3.6.1 VREGENZ
      2. 3.6.2 LDO/VREG
      3. 3.6.3 POR/BOR
      4. 3.6.4 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
      1. 3.8.1 F2838x vs F28P65x GPIO Mux Comparison
    9. 3.9 Analog Multiplexing Changes
      1. 3.9.1 F2838x_176PTP vs F28P65x_176PTP Analog Connections Comparison
  7. 4Application Code Migration From F2838x to F28P65x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5References

Table 2-1 176-Pin PTP Between F2838x and F28P65x
Pin NoPin NameTransition TypeAction
F2838xF28P65xF2838x to F28P65xF28P65x to F2838x
Minor Incompatibility - Signals in Common 1
29ADCINC4ADCINC4/GPIO205Common Analog ChannelUse ADCINC4
30ADCINC3ADCINC3/GPIO206Use ADCINC3
31ADCINC2ADCINC2/AIO237Use ADCINC2
38ADCINA5ADCINA5/AIO232Use ADCINA5
39ADCINA4ADCINA4/AIO231Use ADCINA4
40ADCINA3ADCINA3/AIO230Use ADCINA3
41ADCINA2ADCINA2/AIO229Use ADCINA2
42ADCINA1ADCINA1/AIO228Use ADCINA1
43ADCINA0ADCINA0/AIO227Use ADCINA0
44ADCIN14ADCIN14/AIO225Use ADCIN14
45ADCIN15ADCIN15/AIO226Use ADCIN15
46ADCINB0ADCINB0/AIO233Use ADCINB0
47ADCINB1ADCINB1/AIO234Use ADCINB1
48ADCINB2ADCINB2/AIO235Use ADCINB2
49ADCINB3ADCINB3/AIO236Use ADCINB3
77TDIGPIO222/TDICommon JTAGUse TDI
78TDOGPIO223/TDOUse TDO
92ERRORSTSGPIO224/ERRORSTSCommon ERROR PinUse ERRORSTS
Medium Incompatibility - Different Signals, Same Type
119 NC (no-connect) VREGENZ VREGENZ Function Leave pin floating or tie to VDDIO. The internal pullup on this pin will enable external VREG mode operation on F28P65x which will make it compatible with F2838x
22 GPIO22 ADCINC0/GPIO199 GPIO Function Compatible. Software needs to account for the change in GPIO assignment on these pins. Update code to GPIO199 Update code to GPIO22
23GPIO23ADCINC9/GPIO200Update code to GPIO200Update code to GPIO23
24GPIO24ADCINC8/GPIO201Update code to GPIO201Update code to GPIO24
25GPIO25ADCINC7/GPIO202Update code to GPIO202Update code to GPIO25
27GPIO26ADCINC6/GPIO203Update code to GPIO203Update code to GPIO26
28GPIO27ADCINC5/GPIO204Update code to GPIO204Update code to GPIO27
63GPIO30ADCINA11/GPIO214Update code to GPIO214Update code to GPIO30
64GPIO28ADCINB4/GPIO215Update code to GPIO215Update code to GPIO28
65GPIO29ADCINB5/GPIO216Update code to GPIO216Update code to GPIO29
66GPIO31ADCINB8/GPIO217Update code to GPIO217Update code to GPIO31
67GPIO32ADCINB9/GPIO218Update code to GPIO218Update code to GPIO32
56ADCIND0ADCINB7Analog Function CompatibleUpdate code to ADCINB7Update code to ADCIND0
57ADCIND1ADCINA6Update code to ADCINA6Update code to ADCIND1
58ADCIND2ADCINA7Update code to ADCINA7Update code to ADCIND2
59ADCIND3ADCINA8Update code to ADCINA8Update code to ADCIND3
60ADCIND4ADCINA9Update code to ADCINA9Update code to ADCIND4
Major incompatibility - Different Signals and Types
79TRSTnGPIO30TRSTn FunctionDo not use as GPIO as this has a 2.2k pulldown resistor. The pin should be left as a no-connect. Refer to Section 2.2.1 for more detailsUse as TRSTn pin with a 2.2k pulldown resistor
11VDDIOGPIO22Power to GPIOConnect to 3.3V Supply. Ensure the GPIO is not configured as outputUse as VDDIO
20VDDIOGPIO106
82VDDIOGPIO26
106 VDDIO GPIO105
116VDDIOGPIO32
125VDDIOGPIO27
147VDDIOGPIO104
159VDDIOGPIO24
126VDDGPIO103 Connect to 1.2V Supply. Disable digital input for GPIO. The appropriate bit in the GPIOINENACTRL register must be set to enable the input buffer. See Section 2.2.2 for more details Use as VDD
153VDDGPIO25
158 VDD GPIO31
61VDDADCINA10/GPIO213Power To Analog Option to use the analog channels to monitor VDD, VDDIO, VREFLO or VREFHI signals Use as VDD
20VDDIOADCINC1/GPIO198Use as VDDIO
68VDDIOADCINB10/GPIO219
51VREFLODADCINB11Reference to AnalogUse as analog reference pins
55VREFHIDADCINB6
73FLT1GPIO29Test Pads to GPIO Use as GPIO pins if routed properly in boardUse as test pads
74FLT2GPIO28
(1) Channel to use selected in software