SPRUJ85A April 2024 – August 2024
PRODUCTION DATA
The AM263Px LaunchPad utilizes a 48-pin Ethernet PHY (DP83869HMRGZT) connected to either CPSW RGMII or one on-die Programmable Real-time Unit and Industrial Communication Sub System (PRU-ICSS). The RGMII CPSW port and ICSSM are internally pinmuxed on the AM263Px SoC. For more information on the internal muxing of signals refer to Pinmux Mapping. The PHY is configured to advertise 1-Gb operation. The Ethernet data signals of the PHY are terminated to an RJ45 connector. The RJ45 connector is used on the board for Ethernet 10/100/1000Mbps connectivity with integrated magnetics and LEDs for link and activity indication.
The Ethernet PHY requires three separate power sources. VDDIO is the 3.3V, system generated supply. There are dedicated LDO's for the 1.1V and 2.5V supplies for the Ethernet PHY.
There are series termination resistors on the transmit clock and data signals located near the SoC. There are series termination resistors on the receive clock and data signals near the Ethernet PHY.
The MDIO signal from the SoC to the PHY require 1.5kΩ pullup resistors to the 3.3V system supply voltage for proper operation. There is an analog switch (TS5A23159DGSR) that selects between the CPSW MDIO/MDC and the ICSSM MDIO/MDC signals to be routed to the Ethernet PHY.
AM263Px internal Pinmux is used to select between CPSW RGMII and ICSSM signals. The signals are then routed to a 1:2 mux (TS3DDR3812RUAR) that selects between mapping the signals to the Ethernet PHY or the BP headers in the case that the PRU GPIO signals are being used in a BoosterPack application. There is an AM263Px SoC GPIO select signal that drives the 1:2 mux.
PRU_MUX_SEL | Condition | Function of Mux |
---|---|---|
LOW | Ethernet PHY Selected | Port A ↔ Port B |
HIGH | BoosterPack header Selected | Port A ↔ Port C |
The reset input for the Ethernet PHY is controlled by the WARMRESET AM263Px SoC output signal.
The Ethernet PHY uses many functional pins as strap option to place the device into specific modes of operation.
Functional Pin | Default Mode | Mode in LP | Function |
---|---|---|---|
RX_D0 | 0 | 0 | PHY address: 1100 |
RX_D1 | 0 | 3 | |
JTAG_TDO/GPIO_1 | 0 | 0 | RGMII to Copper |
RX_D3 | 0 | 0 | |
RX_D2 | 0 | 0 | |
LED_0 | 0 | 0 | Auto-negotiation, 1000/100/10 advertised, auto MDI-X |
RX_ER | 0 | 0 | |
LED_2 | 0 | 0 | |
RX_DV | 0 | 0 | Port Mirroring Disabled |