SPRUJ91A april   2023  – may 2023 AM68 , AM68 , AM68A , AM68A , TDA4AL-Q1 , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VE-Q1 , TDA4VL-Q1 , TDA4VL-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Contributions to Power
  5. 2How to Use the Tool
  6. 3Use Case
    1. 3.1 Core Processor Utilization
    2. 3.2 Key IP Frequency Selection
    3. 3.3 Memory Interfaces
    4. 3.4 PHYs
    5. 3.5 High Speed Serial Interface
    6. 3.6 Environmental
    7. 3.7 LVCMOS IOs
    8. 3.8 Buttons
    9. 3.9 Starting Use Case
  7. 4Results Sheet
    1. 4.1 Thermal Power Estimate
    2. 4.2 Peak / PDN Power Estimate
  8. 5Three Specific Pre-Loaded Use Case Results
    1. 5.1 ARM Only
    2. 5.2 Superset
    3. 5.3 Valet Park
  9. 6Summary of Power for Pre-Populated Use Cases
  10. 7Revision History

3.2 Key IP Frequency Selection

This block allows the user to select the frequency for the key blocks in the core utilization block (+DDR).

Note: VPAC / DMPAC – An important note on PLL25. Since the internal frequency of the PLL is limited to -3 GHz, the VPAC and DMPAC cannot simultaneously run at the highest frequency (720 MHz and 520 MHz, respectively) for both IPs.

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