SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
DPLL_VIDEOn May Require Multiple Lock Attempts
Medium
In rare circumstances the DPLL_VIDEO1 and DPLL_VIDEO2 PLLs may not lock on the first attempt during SoC initialization. When this occurs a subsequent attempt to relock the PLL will result in the PLL successfully locking.
In order to successfully lock the PLL, the following software sequence is recommended:
SR 2.0, 1.1, 1.0
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1