CRITICALITY

Medium

DESCRIPTION

The McASP FIFO events to the EDMA or System DMA can be lost depending on the timing between the McASP side activity and the DMA side activity. The problem is most likely to occur in a heavily loaded system which can cause the DMA latency to increase and potentially hit the problematic timing window. When an event is lost, the McASP FIFO Rx path will overflow or the Tx path will underflow. Software intervention is required to recover from this condition.

The issue results due to a state machine boundary condition in the McASP FIFO logic. In normal operation, when "Threshold" (set by the RFIFOCTL[15:8] RNUMEVT and WFIFOCTL[15:8] WNUMEVT registers) words of data are read/written by the DMA then the previous event would be cleared. Similarly, when "Threshold" words of data are written/read from the pins, a new event should be set. If these two conditions occur at the same exact time (within a 2 cycle window), then there is a conflict in the set/clear logic and the event is cleared but is not re-asserted to the DMA.

WORKAROUND

Since the McASP is a real time peripheral, any loss of data due to underflow/overflow should be avoided by eliminating the possibility of DMA read/write completing at the same time as a new McASP Event. Software should configure the system to:

1. Maximize time until the deadline for the McASP FIFO
2. Minimize DMA service time for McASP related transfers

In order to maximize time until deadline, the RNUMEVT and WNUMEVT should be set to the largest multiple of "number of serializers active" that is less-than-equal-to 32 words. Since the FIFO is 64-Words deep, this gives the maximum time to avoid the boundary condition.

In order to minimize DMA service time for McASP related transfers multiple options are possible. For example, McASP buffers can be placed in OCMCRAM or DSP's L2 SRAM (since on chip memories provide a more deterministic and lower latency path compared to DDR memory). In addition, a dedicated Queue/TC can be allocated to McASP transfers. At minimum, care should be taken to avoid any long transfers on the same Queue/TC to avoid head-of-line blocking latency.

REVISIONS IMPACTED

SR 1.1, 1.0

TDA2x: 1.1, 1.0

DRA75x, DRA74x: 1.1, 1.0

AM572x: 1.1