SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
PCIe Preferred PCIe_PHY_RX SCP Register Settings Updated
Low
The “Preferred PCIe_PHY_RX SCP Register Settings” table in version AE and later of the device-specific Technical Reference Manual (TRM) has been updated with values to select fully adaptive equalization and a second-order clock recovery algorithm. These changes have been shown to enhance PCIe receiver (RX) jitter tolerance for 5GT/s operation.
Software can be updated to the new preferred settings, especially for 5GT/s operation, if enhanced RX jitter tolerance is desired.
SR 2.0, 1.1, 1.0
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1