SPRZ450B February   2018  – September 2024 DRA74P , DRA75P , DRA76P , DRA77P

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     Revisions SR 1.0 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i709
    9.     i727
    10.     i729
    11.     i734
    12.     i767
    13.     i782
    14.     i783
    15.     i802
    16.     i803
    17.     i807
    18.     i808
    19.     i809
    20.     i810
    21.     i813
    22.     i814
    23.     i815
    24.     i818
    25.     i819
    26.     i820
    27.     i824
    28.     i826
    29.     i829
    30.     i834
    31.     i849
    32.     i856
    33.     i862
    34.     i863
    35.     i869
    36.     i870
    37.     i871
    38.     i872
    39.     i874
    40.     i878
    41.     i879
    42.     i883
    43.     i889
    44.     i890
    45.     i893
    46.     i896
    47.     i897
    48.     i898
    49.     i899
    50.     i900
    51.     i903
    52.     i904
    53.     i916
    54.     i929
    55.     i930
    56.     i932
    57.     i933
    58.     i936
    59.     i940
    60.     i2446
  4. 3Silicon Limitations
    1.     Revisions SR 1.0 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i844
    7.     i845
    8.     i848
    9.     i876
    10.     i877
    11.     i892
    12.     i909
  5. 4Silicon Cautions
    1.     Revisions SR 1.0 - Cautions List
    2.     i781
    3.     i827
    4.     i832
    5.     i836
    6.     i839
    7.     i864
    8.     i885
    9.     i886
    10.     i912
    11.     i926
    12.     i931
    13.     i935
    14.     i937
  6. 5Revision History

i878

MPU Lockup With Concurrent DMM and EMIF Accesses

CRITICALITY

High

DESCRIPTION

The MPU has two primary paths to DDR and system address space via the MPU Memory Adapter (MPU_MA).

The Low Latency path is the predominant path for DDR accesses and provides direct/low latency/interleaved access to the two EMIFs.

The L3 Interconnect path (via MPU_AXI2OCP bridge) is most typically used for access to non-DDR address space, but is also used for access to DMM and EMIF control registers and to Tiled regions of DDR address space.

Issue is seen to come when there is a heavy memory access through the MPU L3 path, if the MPU is concurrently issuing write transactions via the Low Latency path to DDR and via the L3 Interconnect to the DMM/EMIF/Tiler address space then the transactions can hang and the MPU and DMM/DDR become unresponsive. A device reset is required in order to recover from this condition.

WORKAROUND

In order to completely avoid the issue, the MPU can avoid concurrent accesses to the DMM/EMIF/DDR address space via the Low Latency path and the L3 Interconnect path. In order to accomplish this, the MPU should avoid use of the L3 Interconnect path via the MPU by using DSP, IPU, or DMA to proxy accesses to the EMIF/DMM registers or Tiler DDR address space.

In order to greatly reduce the probability of the issue occurring, the MPU_MA register at 0x482AF400 bits 2 and 1 can be set, that is, 0x482AF400 |= 0x6. With this setting of MPU_MA register, the 3 different heavily loaded application scenario which earlier reproduced the issue was seen working fine for long duration testing.

Note: The MPU_MA register is a valid register address location even though it is located outside the MPU memory space as specified in the device TRM.

REVISIONS IMPACTED

SR 1.0

AM574x: 1.0

DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0

TDA2Px: 1.0

AM576x: 1.0