SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
The common RX FIFO is a 16-bit wide, eight locations deep, first-in-first-out memory buffer if the selected SPI data frame size is greater than 8 bits. The organization of this FIFO is modified dynamically if the selected data size is less than or equal to 8 bits, and for better FIFO utilization behaves as an 8-bit wide, 16 locations deep FIFO. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SPI.RXDATA register.
When configured as a controller (or peripheral), serial data received through the POCI (or PICO) pin is registered before parallel loading into the RX FIFO.