- Single Conversion and Repeat Single Conversion
- Configure STARTADD bits to select the desired MEMCTLx register.
- MEMCTLx is correlated to MEMRESx.
- MEMRESx is correlated to MEMRESIFGx.
- Configure MEMCTL CHANSEL bits to select the desired ADC channel.
- Conversion data is available in MEMRESx.
- MEMRESIFGx can be set to generate a CPU interrupt or the DMA trigger.
- The conversion overflow flag is set when the ADC updates MEMRESx before the previous sample is read by the CPU or DMA.
- The conversion underflow flag is set when the CPU or DMA reads the MEMRESx register before the next conversion result is available.
- Sequence Conversion and Repeat Sequence Conversion
- Configure STARTADD bits to select the first MEMCTL in the sequence.
- Configure ENDADD bits to select the last MEMCTL in the sequence.
- MEMCTLx is correlated to MEMRESIFGx.
- Configure each MEMCTLx CHANSEL bits to select the desired ADC channels.
- Conversion data is available in MEMRESx.
- MEMRESIFGx can be set to generate a CPU interrupt or the DMA trigger.
- The conversion overflow flag is set when the ADC updates MEMRESx before the previous sample is read by the CPU or DMA.
- The conversion underflow flag is set when the CPU or DMA reads the MEMRESx register before the next conversion result is available.
Note: For DMA based operation, the MEMCTL start address should be smaller than the end address for single sequence conversion as DMA source does not roll back. Repeat sequence conversion mode does not support DMA based data transfer because the DMA does not support circular addressing mode.