SWCU193A April   2023  – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 Flash
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  4. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 Reset
      2. 6.4.2 Shutdown
      3. 6.4.3 Active
      4. 6.4.4 Idle
      5. 6.4.5 Standby
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  9. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 Flash
        1. 7.2.4.1 Flash Read-Only Protection
        2. 7.2.4.2 Flash Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  10. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 8.2.4.5 Debug Flow Charts
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  11. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  12. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Deadband
      6. 10.4.6 Deadband, Fault, and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  13. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  14. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  15. 13Low Power Comparator and SYS0
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-Up
    4. 13.4 SYS0 Registers
  16. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  17. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  18. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  19. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power-Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA and FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-Hoc Single Conversion
    5. 17.5 ADC Registers
  20. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  21. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  22. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  23. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  24. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-Domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers
  25. 23Revision History

19.3.7 Interrupts

The UART can generate interrupts when the following conditions are observed:

  • Overrun error
  • Break error
  • Parity error
  • Framing error
  • Receive time-out
  • Transmit (when the condition defined in the UART:IFLS TXSEL register bit is met)
  • Receive (when the condition defined in the UART:IFLS RXSEL register bit is met)
  • End of transmission (when no data on the TX line and TX FIFO underflow
  • RX DMA Done
  • TX DMA Done

All of the interrupt events are ORed together before being sent to the MCU event fabric, so the UART can only generate a single interrupt request at any given time. The software can service multiple interrupt events in a single interrupt service routine (ISR) by reading the UART Masked Interrupt Status Register (UART.MIS).

The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask Register (UART.IMSC) by setting the corresponding bits. If interrupts are not used, the raw interrupt status is always visible through the UART Raw Interrupt Status Register (UART.RIS).

Interrupts can be cleared (for the UART.MIS and UART.RIS registers) by setting the corresponding bit in the UART Interrupt Clear Register (UART.ICR).

The receive time-out interrupt is asserted when the RX FIFO is not empty, and no further data is received over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when the corresponding bit in the UART.ICR register is set.

The UART module provides the possibility of setting and clearing masks for every individual interrupt source using the UART Interrupt Mask Set/Clear Register (UART.IMSC). The five events that can cause combined interrupts to CPU are:

  • RX: The receive interrupt changes state when one of the following events occurs:
    • If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level. When this happens, the receive interrupt is asserted high. The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt.
    • If the FIFOs are disabled (have a depth of one location) and data is received, thereby filling the location, the receive interrupt is asserted high. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt.
  • TX: The transmit interrupt changes state when one of the following events occurs:
    • If the FIFOs are enabled and the transmit FIFO is equal to or lower than the programmed trigger level, then the transmit interrupt is asserted high. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt.
    • If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitter's single location, the transmit interrupt is asserted high. The interrupt is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt.
  • RX time-out: The receive time-out interrupt is asserted when the receive FIFO is not empty, and no more data is received during a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when 1 is written to the corresponding bit of the Interrupt Clear Register (UART:ICR).
  • Modem status: The modem status interrupt is asserted if the modem status signal CTS toggles. It can be cleared using the corresponding clear bit in the UART.ICR register.
  • Error: The error interrupt is asserted when an error occurs in the reception of data by the UART. The interrupt can be caused by a number of different error conditions:
    • framing
    • parity
    • break
    • overrun

The cause of the interrupt can be determined by reading the UART.RIS register or the UART.MIS register. The interrupt can be cleared by writing to the relevant bits of the UART.ICR register.

In addition to the five events produced by the UART module, two additional events are ORed to the interrupt line:

  • RX DMA done: Indicates that the receiver µDMA task is completed. This is a level interrupt provided by the µDMA module.
  • TX DMA done: Indicates that the transmit µDMA task is completed. This is a level interrupt provided by the µDMA module.