SWRA640H December 2018 – May 2024 CC1310 , CC1312R , CC1314R10 , CC1350 , CC1352P , CC1352R , CC1354P10 , CC1354R10 , CC2620 , CC2630 , CC2640 , CC2640R2F , CC2640R2F-Q1 , CC2642R , CC2642R-Q1 , CC2650 , CC2652P , CC2652R , CC2652R7 , CC2652RB , CC2652RSIP , CC2674P10 , CC2674R10
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface. The 2-pin cJTAG mode using only TCK and TMS I/O pads is the default configuration after power up. The 4-pin JTAG uses TCK, TMS, TDI, and TDO.
Signal | 8 x 8 QFN (RSK) | 7 × 7 QFN (RGZ) | 5 × 5 QFN (RHB) | WCSP (YFV) | 4 × 4 QFN (RSM) |
---|---|---|---|---|---|
TCK | Pin 25 | Pin 25 | Pin 14 | Pin F2 | Pin 14 |
TMS | Pin 24 | Pin 24 | Pin 13 | Pin E4 | Pin 13 |
TDI | DIO17 | DIO17 | DIO6 | DIO6 | DIO4 |
TDO | DIO16 | DIO16 | DIO5 | DIO5 | DIO3 |