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High Speed SAR ADCs incorporate precision features (for example, excellent DC linearity and AC performance) while also allowing for sampling rates above 10 MSPS at ultra-low power consumption. With higher sampling speeds comes higher output data rates, so FPGA's are typically used to handle these higher speed CMOS and LVDS interfaces. However, there are trade-offs that can be made to reduce data rates and pin count while maintaining (or improving) the performance your application demands which can open the door for lower cost ADC data capture solutions (micro controllers and low cost FPGAs).
The CMOS interface is very common for high-speed data converters, and we typically see a maximum rate of 250 Mbps for CMOS interface. While the ADC36XX family also offers LVDS output data (see ADC3683 and ADC3663), this section focuses primarily on the CMOS interface of the ADC3643 and ADC3541, and trade-offs to consider when optimizing your application.
The ADC3643 and ADC3541 can be configured in a parallel or serial CMOS mode. Both of these modes have unique features, so it is important to understand both accordingly.
Parallel CMOS output is the most common method of implementation for high-speed CMOS ADCs. However, there are different Parallel CMOS implementations, like SDR (Single Data Rate) and DDR (Dual Data Rate), and both have implications on either data rate or pin count. Due to the nature of the CMOS output, a series resistance is needed to control the current output and ensure signal integrity, so reducing the number of output pins will correspondingly reduce the amount of series resistors.