SBAA653 October 2024 ADC3641 , ADC3642 , ADC3643 , ADC3661 , ADC3662 , ADC3663 , ADC3681 , ADC3682 , ADC3683 , LMK04368-EP , LMK04832 , LMK04832-SEP , LMK04832-SP , LMX1204 , LMX1205 , LMX1860-SEP , LMX1906-SP , LMX2571 , LMX2571-EP , LMX2572 , LMX2572LP , LMX2594 , LMX2595 , LMX2615-SP , LMX2694-EP , LMX2694-SEP , LMX2820
There are many deliberations when creating designs with high-speed analog-to-digital converters, or ADC. Understanding the ADC sampling clocking is just one of these deliberations which is paramount to making sure your design requirements are met. There are several metrics that need to be understood about the ADC sampling clock that have a direct effect on the ADC performance (or signal-to-noise ratio, SNR) as discussed in the analog design journal article Clock jitter analyzed in the time domain Part 1, Part 2, and Part 3. However, from a practical stand point, what does that mean? In this application note, numerous experiments and tradeoffs are uncovered and proven on the bench to give better insight for your next high-speed ADC clock design.
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In this application note, the tradeoffs of different clocking parameters are uncovered and proven on the bench. This demonstrates different common behaviors to avoid common pitfalls when designing your clock tree on your next high-speed converter design. Some relationships seen include the effect of the clock performance when increasing the analog input frequency, the clock slew rate's effect on the performance of the ADC, and so on.