The TPS2388x is an 8-channel power sourcing equipment (PSE) controller engineered to insert power onto Ethernet cables in accordance with the IEEE 802.3bt standard. Programmable SRAM enables the in-field firmware upgradability over I2C. This provides maximum interoperability with the latest PoE enabled devices.
Before sending commands to the TPS2388x, the first thing after power up is to load the SRAM and Parity code. Table 1 provides the steps to load the code.
If there is more than one TPS2388x device in the system, use a global I2C write to load the SRAM and parity code to multiple devices through the global I2C address 0x7F.
Delay the SRAM and parity programming at least 50 ms from the initial power on (VPWR and VDD above UVLO) of the device to allow for the device to complete the internal hardware initialization process.
The following procedure applies for either 8-bit (configuration A) or 16-bit (configuration B) I2C operation. The SRAM and parity programming control must be completed at the lower I2C address (Channels 1-4). Configuring SRAM control registers for the upper I2C device address (Channels 5-8) does not program the SRAM or parity.
Access the latest version of the TPS2388x firmware from the TI mySecure Software web page.
Command | Register | Data | Comments | If Parity Disabled | |
---|---|---|---|---|---|
Step 1 | Write | 0x60 | 0x01 | Reset the memory address pointer | |
Step 2 | Write | 0x62 | 0x00 | Set start address LSB | |
Step 3 | Write | 0x63 | 0x80 | Set start address MSB | |
Step 4 | Write | 0x60 | 0xC4 | Reset CPU and enable Parity Write | Skip |
Step 5 | Write | 0x1D |
0xBC | Preparing for RAM download |
Skip |
Step 6 | Write | 0xD7 | 0x02 | ||
Step 7 | Write |
0x91 | 0x00 | ||
Step 8 | Write | 0x90 | 0x00 | ||
Step 9 | Write | 0xD7 | 0x00 | ||
Step 10 | Write | 0x1D | 0x00 | ||
Step 11 | Write | 0x61 | xx,xx,xx,... | Load Parity data | Skip |
After all data is written: | |||||
Step 12 | Write | 0x60 | 0xC5 | Keep CPU in reset and reset memory pointer | Skip |
Step 13 | Write | 0x62 | 0x00 | Reset LSB of start address | Skip |
Step 14 | Write | 0x63 | 0x80 | Reset MSB of start address | Skip |
Step 15 | Write | 0x60 | 0xC0 | Keep CPU in reset and enable SRAM I2C write | |
Step 16 | Write | 0x1D |
0xBC | Preparing for RAM download | Skip if already run as part of Steps 5-10 |
Step 17 | Write | 0xD7 |
0x02 | ||
Step 18 | Write | 0x91 |
0x00 | ||
Step 19 | Write | 0x90 |
0x00 | ||
Step 20 | Write | 0xD7 | 0x00 | ||
Step 21 | Write | 0x1D | 0x00 | ||
Step 22 | Write | 0x61 | xx,xx,xx,... | Load SRAM data | |
Step 23 | Write | 0x60 | 0x18 | Clears CPU reset and enables SRAM and Parity | Write ‘0x08’ instead |
Step 24 | Delay for approximately 12 ms | ||||
Step 25 | Read | 0x41 | Check firmware version |
Here are the instructions to reload the SRAM and parity code when the device is in safe mode.
Command | Register | Data | Comments | If Parity Disabled | |
---|---|---|---|---|---|
Step 1 | Write | 0x60 | 0x01 | Reset the memory address pointer | |
Step 2 | Write | 0x62 | 0x00 | Set start address LSB | |
Step 3 | Write | 0x63 | 0x80 | Set start address MSB | |
Step 4 | Write | 0x60 | 0x84 | Enable Parity write | Skip |
Step 5 | Write | 0x1D |
0xBC | Preparing for RAM download | Skip |
Step 6 | Write | 0xD7 | 0x02 | ||
Step 7 | Write | 0x91 | 0x00 | ||
Step 8 | Write | 0x90 | 0x00 | ||
Ste 9 | Write | 0xD7 | 0x00 | ||
Step 10 | Write | 0x1D | 0x00 | ||
Step 11 | Write | 0x61 | xx,xx,xx,... | Load Parity data | Skip |
After all data is written: | |||||
Step 12 | Write | 0x60 | 0x85 | Reset memory pointer | Skip |
Step 13 | Write | 0x62 | 0x00 | Reset LSB of start address | Skip |
Step 14 | Write | 0x63 | 0x80 | Reset MSB of start address | Skip |
Step 15 | Write | 0x60 | 0x80 | Enable SRAM I2C write | |
Step 16 | Write | 0x1D | 0xBC | Preparing for RAM download | Skip if already run as part of Steps 5-10 |
Step 17 | Write | 0xD7 | 0x02 | ||
Step 18 | Write | 0x91 | 0x00 | ||
Step 19 | Write | 0x90 | 0x00 | ||
Step 20 | Write | 0xD7 | 0x00 | ||
Step 21 | Write | 0x1D | 0x00 | ||
Step 22 | Write | 0x61 | xx, xx, xx, ... | Load SRAM data | |
Step 23 | Write | 0x60 | 0x18 | Enables SRAM and Parity | Write ‘0x08’ instead |
Step 24 | Delay for approximately 12 ms | ||||
Step 25 | Read | 0x41 | Check firmware version |
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