SNAS676D October 2015 – October 2017 LMK61A2-100M , LMK61A2-125M , LMK61A2-156M , LMK61A2-312M , LMK61A2-644M , LMK61E0-050M , LMK61E0-155M , LMK61E0-156M , LMK61E2-100M , LMK61E2-125M , LMK61E2-156M , LMK61E2-312M , LMK61I2-100M
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The LMK61XX is an ultra-low jitter oscillator that generates a commonly used reference clock. The device is pre-programmed in factory to support any reference clock frequency; supported output formats are LVPECL up to 1 GHz, LVDS up to 900 MHz, and HCSL up to 400 MHz. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.
Changes from C Revision (September 2017) to D Revision
Changes from B Revision (March 2017) to C Revision
Changes from A Revision (November 2015) to B Revision
Changes from * Revision (October 2015) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
POWER | |||
GND | 3 | Ground | Device Ground. |
VDD | 6 | Analog | 3.3 V Power Supply. |
OUTPUT BLOCK | |||
OUTP, OUTN | 4, 5 | Universal | Differential Output Pair (LVPECL, LVDS or HCSL). |
DIGITAL CONTROL / INTERFACES | |||
NC | 2 | N/A | No Connect. |
OE | 1 | LVCMOS | Output Enable (internal pullup). When set to low, output pair is disabled and set at high impedance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Device supply voltage | –0.3 | 3.6 | V |
VIN | Output voltage for logic inputs | –0.3 | VDD + 0.3 | V |
VOUT | Output voltage for clock outputs | –0.3 | VDD + 0.3 | V |
TJ | Junction temperature | 150 | °C | |
TSTG | Storage temperature | –40 | 125 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VDD | Device supply voltage | 3.135 | 3.3 | 3.465 | V | |
TA | Ambient temperature | –40 | 25 | 85 | °C | |
TJ | Junction temperature | LMK61X2 | 125 | °C | ||
LMK61X0 | 115 | °C | ||||
tRAMP | VDD power-up ramp time | 0.1 | 100 | ms |
THERMAL METRIC(1) | LMK61XX (2) (3) (4) | UNIT | |||
---|---|---|---|---|---|
SIA (QFM) | |||||
6 PINS | |||||
Airflow (LFM) 0 | Airflow (LFM) 200 | Airflow (LFM) 400 | |||
RθJA | Junction-to-ambient thermal resistance | 55.2 | 46.4 | 43.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 34.6 | n/a | n/a | °C/W |
RθJB | Junction-to-board thermal resistance | 37.7 | n/a | n/a | °C/W |
ψJT | Junction-to-top characterization parameter | 11.3 | 17.6 | 22.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 37.7 | 41.5 | 40.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | n/a | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IDD | Device current consumption | LVPECL(2) | 162 | 208 | mA | |
LVDS | 152 | 196 | ||||
HCSL | 155 | 196 | ||||
IDD-PD | Device current consumption when output is disabled | OE = GND | 136 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fOUT | Output frequency(2) | 10 | 1000 | MHz | ||
VOD | Output voltage swing (VOH – VOL)(2) |
700 | 800 | 1200 | mV | |
VOUT, DIFF, PP | Differential output peak-to-peak swing | 2 × |VOD| | V | |||
VOS | Output common-mode voltage | VDD – 1.55 | V | |||
tR / tF | Output rise/fall time (20% to 80%)(3) | 120 | 200 | ps | ||
PN-Floor | Output phase noise floor (fOFFSET > 10 MHz) | 156.25 MHz | –165 | dBc/Hz | ||
ODC | Output duty cycle(3) | 45% | 55% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fOUT | Output frequency(1) | 10 | 900 | MHz | ||
VOD | Output voltage swing (VOH – VOL)(1) |
300 | 390 | 480 | mV | |
VOUT, DIFF, PP | Differential output peak-to-peak swing | 2 × |VOD| | V | |||
VOS | Output common-mode voltage | 1.2 | V | |||
tR / tF | Output rise/fall time (20% to 80%)(2) | 150 | 250 | ps | ||
PN-Floor | Output phase noise floor (fOFFSET > 10 MHz) | 156.25 MHz | –162 | dBc/Hz | ||
ODC | Output duty cycle(2) | 45% | 55% | |||
ROUT | Differential output impedance | 125 | Ohm |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fOUT | Output frequency | 10 | 400 | MHz | ||
VOH | Output high voltage | 600 | 850 | mV | ||
VOL | Output low voltage | –100 | 100 | mV | ||
VCROSS | Absolute crossing voltage(2)(3) | 250 | 475 | mV | ||
VCROSS-DELTA | Variation of VCROSS(2)(3) | 0 | 140 | mV | ||
dV/dt | Slew rate(4) | 0.8 | 2 | V/ns | ||
PN-Floor | Output phase noise floor (fOFFSET > 10 MHz) | 100 MHz | –164 | dBc/Hz | ||
ODC | Output duty cycle(4) | 45% | 55% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | Input high voltage | 1.4 | V | |||
VIL | Input low voltage | 0.6 | V | |||
IIH | Input high current | VIH = VDD | –40 | 40 | uA | |
IIL | Input low current | VIL = GND | –40 | 40 | uA | |
CIN | Input capacitance | 2 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fT | Total frequency tolerance | LMK61X2: All output formats, frequency bands and device junction temperature up to 125°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (10 years) | –50 | 50 | ppm | |
LMK61X0: All output formats, frequency bands and device junction temperature up to 115°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (5 years at 40°C) | –25 | 25 | ppm |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VTHRESH | Threshold voltage(1) | 2.72 | 2.95 | V | ||
VDROOP | Allowable voltage droop(2) | 0.1 | V | |||
tSTARTUP | Start-up time (1) | Time elapsed from VDD at 3.135 V to output enabled | 10 | ms | ||
tOE-EN | Output enable time(2) | Time elapsed from OE at VIH to output enabled | 50 | us | ||
tOE-DIS | Output disable time(2) | Time elapsed from OE at VIL to output disabled | 50 | us |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PSRR | Spurs induced by 50-mV power supply ripple(2)(3) at 156.25-MHz output, all output types | Sine wave at 50 kHz | –70 | dBc | ||
Sine wave at 100 kHz | –70 | |||||
Sine wave at 500 kHz | –70 | |||||
Sine wave at 1 MHz | –70 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RJ | RMS phase jitter(2)
(12 kHz – 20 MHz) (1 kHz – 5 MHz) |
fOUT < 100 MHz, all output types | 200 | 300 | fs RMS | |
RJ | RMS phase jitter(2)
(12 kHz – 20 MHz) (1 kHz – 5 MHz) |
fOUT ≥ 100 MHz (except 155.52 MHz and 644.53125 MHz), all output types | 100 | 200 | fs RMS | |
RJ | RMS phase jitter(2)
(12 kHz – 20 MHz) (1 kHz – 5 MHz) |
fOUT = 155.52 MHz or 644.53125 MHz, all output types | 150 | 300 | fs RMS |
PARAMETER | OUTPUT TYPE | UNITS | |||
---|---|---|---|---|---|
LVPECL | LVDS | HCSL | |||
phn10k | Phase noise at 10-kHz offset | –143 | –143 | –143 | dBc/Hz |
Phn20k | Phase noise at 20-kHz offset | –143 | –143 | –143 | dBc/Hz |
phn100k | Phase noise at 100-kHz offset | –144 | –144 | –144 | dBc/Hz |
Phn200k | Phase noise at 200-kHz offset | –145 | –145 | –145 | dBc/Hz |
phn1M | Phase noise at 1-MHz offset | –150 | –150 | –150 | dBc/Hz |
phn2M | Phase noise at 2-MHz offset | –154 | –154 | –154 | dBc/Hz |
phn10M | Phase noise at 10-MHz offset | –165 | –162 | –164 | dBc/Hz |
phn20M | Phase noise at 20-MHz offset | –165 | –162 | –164 | dBc/Hz |
PARAMETER | CONDITION / TEST METHOD |
---|---|
Mechanical Shock | MIL-STD-202, Method 213 |
Mechanical Vibration | MIL-STD-202, Method 204 |
Moisture Sensitivity Level | J-STD-020, MSL3 |