SLAS859C May 2012 – May 2015 PCM5100A , PCM5100A-Q1 , PCM5101A , PCM5101A-Q1 , PCM5102A , PCM5102A-Q1
PRODUCTION DATA.
The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.
Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.
The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.
The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.
Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.
Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
PCM5102A | TSSOP (20) | 5.50 mm × 4.40 mm |
PCM5101A | ||
PCM5100A |
Changes from B Revision (January 2015) to C Revision
Changes from A Revision (September 2012) to B Revision
Changes from * Revision (May 2012) to A Revision
PART NUMBER | DYNAMIC RANGE | SNR | THD |
---|---|---|---|
PCM5102A | 112dB | 112dB | –93 dB |
PCM5101A | 106 dB | 106 dB | –92 dB |
PCM5100A | 100 dB | 100 dB | –90 dB |
PARAMETER | PCM5102 / PCM5101 / PCM5100 |
SNR | 112 / 106 / 100 dB |
Dynamic range | 112 /106 / 100 dB |
THD+N at –1 dBFS | –93/ –92 / –90 dB |
Full-scale single-ended output | 2.1 VRMS (GND center) |
Normal 8× oversampling digital filter latency | 20tS |
Low latency 8× oversampling digital filter latency | 3.5tS |
Sampling frequency | 8 kHz to 384 kHz |
System clock multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072 | Up to 50 MHz |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 9 | — | Analog ground |
AVDD | 8 | P | Analog power supply, 3.3 V |
BCK | 13 | I | Audio data bit clock input(1) |
CAPM | 4 | O | Charge pump flying capacitor terminal for negative rail |
CAPP | 2 | O | Charge pump flying capacitor terminal for positive rail |
CPGND | 3 | — | Charge pump ground |
CPVDD | 1 | P | Charge pump power supply, 3.3 V |
DEMP | 10 | I | De-emphasis control for 44.1-kHz sampling rate(1): Off (Low) / On (High) |
DGND | 19 | — | Digital ground |
DIN | 14 | I | Audio data input(1) |
DVDD | 20 | P | Digital power supply, 1.8 V or 3.3 V |
FLT | 11 | I | Filter select : Normal latency (Low) / Low latency (High) |
FMT | 16 | I | Audio format selection : I2S (Low) / Left-justified (High) |
LDOO | 18 | P | Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal |
LRCK | 15 | I | Audio data word clock input(1) |
OUTL | 6 | O | Analog output from DAC left channel |
OUTR | 7 | O | Analog output from DAC right channel |
SCK | 12 | I | System clock input(1) |
VNEG | 5 | O | Negative charge pump rail terminal for decoupling, –3.3 V |
XSMT | 17 | I | Soft mute control(1): Soft mute (Low) / soft un-mute (High) |