SLAS859C May 2012 – May 2015 PCM5100A , PCM5100A-Q1 , PCM5101A , PCM5101A-Q1 , PCM5102A , PCM5102A-Q1
PRODUCTION DATA.
The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.
Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.
The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.
The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.
Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.
Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
PCM5102A | TSSOP (20) | 5.50 mm × 4.40 mm |
PCM5101A | ||
PCM5100A |
Changes from B Revision (January 2015) to C Revision
Changes from A Revision (September 2012) to B Revision
Changes from * Revision (May 2012) to A Revision
PART NUMBER | DYNAMIC RANGE | SNR | THD |
---|---|---|---|
PCM5102A | 112dB | 112dB | –93 dB |
PCM5101A | 106 dB | 106 dB | –92 dB |
PCM5100A | 100 dB | 100 dB | –90 dB |
PARAMETER | PCM5102 / PCM5101 / PCM5100 |
SNR | 112 / 106 / 100 dB |
Dynamic range | 112 /106 / 100 dB |
THD+N at –1 dBFS | –93/ –92 / –90 dB |
Full-scale single-ended output | 2.1 VRMS (GND center) |
Normal 8× oversampling digital filter latency | 20tS |
Low latency 8× oversampling digital filter latency | 3.5tS |
Sampling frequency | 8 kHz to 384 kHz |
System clock multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072 | Up to 50 MHz |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 9 | — | Analog ground |
AVDD | 8 | P | Analog power supply, 3.3 V |
BCK | 13 | I | Audio data bit clock input(1) |
CAPM | 4 | O | Charge pump flying capacitor terminal for negative rail |
CAPP | 2 | O | Charge pump flying capacitor terminal for positive rail |
CPGND | 3 | — | Charge pump ground |
CPVDD | 1 | P | Charge pump power supply, 3.3 V |
DEMP | 10 | I | De-emphasis control for 44.1-kHz sampling rate(1): Off (Low) / On (High) |
DGND | 19 | — | Digital ground |
DIN | 14 | I | Audio data input(1) |
DVDD | 20 | P | Digital power supply, 1.8 V or 3.3 V |
FLT | 11 | I | Filter select : Normal latency (Low) / Low latency (High) |
FMT | 16 | I | Audio format selection : I2S (Low) / Left-justified (High) |
LDOO | 18 | P | Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal |
LRCK | 15 | I | Audio data word clock input(1) |
OUTL | 6 | O | Analog output from DAC left channel |
OUTR | 7 | O | Analog output from DAC right channel |
SCK | 12 | I | System clock input(1) |
VNEG | 5 | O | Negative charge pump rail terminal for decoupling, –3.3 V |
XSMT | 17 | I | Soft mute control(1): Soft mute (Low) / soft un-mute (High) |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | AVDD, CPVDD, DVDD | –0.3 | 3.9 | V |
LDO with DVDD at 1.8 V | –0.3 | 2.25 | ||
Digital input voltage | DVDD at 1.8 V | –0.3 | 2.25 | |
DVDD at 3.3 V | –0.3 | 3.9 | ||
Analog input voltage | –0.3 | 3.9 | ||
Operating junction temperature range | –40 | 130 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
AVDD | Analog power supply voltage range | Referenced to AGND(1) | VCOM mode | 3 | 3.3 | 3.46 | V |
VREF mode | 3.2 | 3.3 | 3.46 | ||||
DVDD | Digital power supply voltage range | Referenced to DGND(1) | 1.8 V DVDD | 1.65 | 1.8 | 1.95 | V |
3.3 V DVDD | 3.1 | 3.3 | 3.46 | ||||
CPVDD | Charge pump supply voltage range | Referenced to CPGND(1) | 3.1 | 3.3 | 3.46 | V | |
MCLK | Master clock frequency | 50 | MHz | ||||
LOL, LOR | Stereo line output load resistance | 1 | 10 | kΩ | |||
CLOUT | Digital output load capacitance | 10 | pF | ||||
TJ | Operating junction temperature range | –40 | 130 | °C |
THERMAL METRIC(1) | PW | UNIT | |
---|---|---|---|
20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 91.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 25.3 | |
RθJB | Junction-to-board thermal resistance | 42 | |
ψJT | Junction-to-top characterization parameter | 1 | |
ψJB | Junction-to-board characterization parameter | 41.5 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Resolution | 16 | 24 | 32 | Bits | |||
Data Format (PCM Mode) | |||||||
Audio data bit length | 16 | 24 | 32 | Bits | |||
fS(7) | Sampling frequency | 8 | 384 | kHz | |||
fSCK | System clock frequency | Clock multiples: 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 | 50 | MHz | |||
Digital Input/Output for non-Q1 Consumer Grade Devices | |||||||
Logic family: 3.3 V LVCMOS compatible | |||||||
VIH | Input logic level | 0.7×DVDD | V | ||||
VIL | 0.3×DVDD | ||||||
IIH | Input logic current | VIN = VDD | 10 | µA | |||
IIL | VIN = 0 V | –10 | |||||
VOH | Output logic level | IOH = –4 mA | 0.8×DVDD | V | |||
VOL | IOL = 4 mA | 0.22×DVDD | |||||
Logic family 1.8 V LVCMOS compatible | |||||||
VIH | Input logic level | 0.7×DVDD | V | ||||
VIL | 0.3×DVDD | ||||||
IIH | Input logic current | VIN = VDD | 10 | µA | |||
IIL | VIN = 0 V | –10 | |||||
VOH | Output logic level | IOH = –2 mA | 0.8×DVDD | V | |||
VOL | IOL = 2 mA | 0.22×DVDD | |||||
Digital Input/Output for Q1 Automotive Grade Devices | |||||||
Logic family: 3.3 V LVCMOS compatible | |||||||
VIH | Input logic level | 0.7×DVDD | V | ||||
VIL | 0.3×DVDD | ||||||
IIH | Input logic current | VIN = VDD | 10 | µA | |||
IIL | VIN = 0 V | –10 | |||||
VOH | Output logic level | IOH = –4 mA | 0.8×DVDD | V | |||
VOL | IOL = 4 mA | 0.22×DVDD | |||||
Logic family 1.8 V LVCMOS compatible | |||||||
VIH | Input logic level | 0.7×DVDD | V | ||||
VIL | 0.3×DVDD | ||||||
IIH | Input logic current | VIN = VDD | 10 | µA | |||
IIL | VIN = 0 V | –10 | |||||
VOH | Output logic level | IOH = –2 mA | 0.8×DVDD | V | |||
VOL | IOL = 2 mA | 0.3×DVDD | |||||
Dynamic Performance (PCM Mode)(1)(2) | |||||||
THD+N at –1 dBFS(2) | fS = 48 kHz | PCM5102A | –93 | –83 | dB | ||
PCM5101A | –92 | –82 | |||||
PCM5100A | –90 | –80 | |||||
fS = 96 kHz and 192 kHz | PCM5102A | –93 | |||||
PCM5101A | –92 | ||||||
PCM5100A | –90 | ||||||
Dynamic range(2) | EIAJ, A-weighted, fS = 48 kHz | PCM5102A | 106 | 112 | |||
PCM5101A | 100 | 106 | |||||
PCM5100A | 95 | 100 | |||||
EIAJ, A-weighted, fS = 96 kHz and 192 kHz | PCM5102A | 112 | |||||
PCM5101A | 106 | ||||||
PCM5100A | 100 | ||||||
Signal-to-noise ratio(2) | EIAJ, A-weighted, fS = 48 kHz | PCM5102A | 112 | ||||
PCM5101A | 106 | ||||||
PCM5100A | 100 | ||||||
EIAJ, A-weighted, fS = 96 kHz and 192 kHz | PCM5102A | 112 | |||||
PCM5101A | 106 | ||||||
PCM5100A | 100 | ||||||
Signal to noise ratio with analog mute(2)(3) | EIAJ, A-weighted, fS = 48 kHz | 113 | 123 | ||||
EIAJ, A-weighted, fS = 96 kHz and 192 kHz | 123 | ||||||
Channel separation | fS = 48 kHz | PCM5102A | 100 | 109 | |||
PCM5101A | 95 | 103 | |||||
PCM5100A | 90 | 97 | |||||
fS = 96 kHz | PCM5102A | 109 | |||||
PCM5101A | 103 | ||||||
PCM5100A | 97 | ||||||
fS = 192 kHz | PCM5102A | 109 | |||||
PCM5101A | 103 | ||||||
PCM5100A | 97 | ||||||
Analog Output | |||||||
Output voltage | 2.1 | VRMS | |||||
Gain error | –6 | ±2 | 6 | % of FSR | |||
Gain error on Q1 Automotive Grade Devices | –7 | ±2 | 7 | % of FSR | |||
Gain mismatch, channel-to-channel | –6 | ±2 | 6 | % of FSR | |||
Gain mismatch, channel-to-channel on Q1 Devices | –6 | ±2 | 6 | % of FSR | |||
PCM5100/1 bipolar zero error | At bipolar zero | –5 | ±1 | 5 | mV | ||
PCM5102 Bipolar zero error | At bipolar zero | –2 | ±1 | 2 | mV | ||
Load impedance | 1 | kΩ | |||||
Filter Characteristics–1: Normal | |||||||
Pass band | 0.45fS | ||||||
Stop band | 0.55fS | ||||||
Stop band attenuation | –60 | dB | |||||
Pass-band ripple | ±0.02 | ||||||
Delay time | 20tS | s | |||||
Filter Characteristics–2: Low Latency | |||||||
Pass band | 0.47fS | ||||||
Stop band | 0.55fS | ||||||
Stop band attenuation | –52 | dB | |||||
Pass-band ripple | ±0.0001 | ||||||
Delay time | 3.5tS | s | |||||
Power Supply Requirements | |||||||
DVDD | Digital supply voltage | Target DVDD = 1.8 V | 1.65 | 1.8 | 1.95 | VDC | |
DVDD | Digital supply voltage | Target DVDD = 3.3 V | 3 | 3.3 | 3.6 | VDC | |
AVDD | Analog supply voltage | 3 | 3.3 | 3.6 | |||
CPVDD | Charge-pump supply voltage | 3 | 3.3 | 3.6 | |||
IDD | DVDD supply current at 1.8 V(4) | fS = 48 kHz | 7 | mA | |||
fS = 96 kHz | 8 | ||||||
fS = 192 kHz | 9 | ||||||
IDD | DVDD supply current at 1.8 V(5) | fS = 48 kHz | 7 | mA | |||
fS = 96 kHz | 8 | ||||||
fS = 192 kHz | 9 | ||||||
IDD | DVDD supply current at 1.8 V(6) | Standby | 0.3 | mA | |||
IDD | DVDD supply current at 3.3 V(4) | fS = 48 kHz | 7 | 12 | mA | ||
fS = 96 kHz | 8 | ||||||
fS = 192 kHz | 9 | ||||||
IDD | DVDD supply current at 3.3 V(5) | fS = 48 kHz | 8 | 13 | mA | ||
fS = 96 kHz | 9 | ||||||
fS = 192 kHz | 10 | ||||||
IDD | DVDD supply current at 3.3 V(6) | Standby | 0.5 | 0.8 | mA | ||
IDD | AVDD / CPVDD supply current(4) | fS = 48 kHz | 11 | 16 | mA | ||
fS = 96 kHz | 11 | ||||||
fS = 192 kHz | 11 | ||||||
IDD | AVDD / CPVDD supply current(5) | fS = 48 kHz | 22 | 32 | mA | ||
fS = 96 kHz | 22 | ||||||
fS = 192 kHz | 22 | ||||||
IDD | AVDD / CPVDD supply current(6) | fS = n/a | 0.2 | 0.4 | mA | ||
Power dissipation, DVDD = 1.8 V(4) | fS = 48 kHz | 49 | 185 | mW | |||
fS = 96 kHz | 51 | ||||||
fS = 192 kHz | 53 | ||||||
Power dissipation, DVDD = 1.8 V(5) | fS = 48 kHz | 85 | 187 | mW | |||
fS = 96 kHz | 87 | ||||||
fS = 192 kHz | 89 | ||||||
Power dissipation, DVDD = 1.8 V(6) | fS = n/a (Power Down Mode) | 1 | mW | ||||
Power dissipation, DVDD = 3.3 V(4) | fS = 48 kHz | 60 | 92.4 | mW | |||
fS = 96 kHz | 63 | ||||||
fS = 192 kHz | 66 | ||||||
Power dissipation, DVDD = 3.3 V(5) | fS = 48 kHz | 99 | 148.5 | mW | |||
fS = 96 kHz | 102 | ||||||
fS = 192 kHz | 106 | ||||||
Power dissipation, DVDD = 3.3 V(6) | fS = n/a (Power Down Mode) | 2 | 4 | mW |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
tSCY | System clock pulse cycle time | 20 | 1000 | ns | ||
tSCKH | System clock pulse width, High | DVDD = 1.8 V | 8 | ns | ||
DVDD = 3.3 V | 9 | |||||
tSCKL | System clock pulse width, Low | DVDD = 1.8 V | 8 | ns | ||
DVDD = 3.3 V | 9 |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
tr | Rise time | 20 | ns | ||
tf | Fall time | 20 | ns |
The integrated PLL on the device provided adds the flexibility to remove the system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.
Powersense undervoltage protection utilizes a two-level mute system. Upon clock error or system power failure, the device digitally attenuates the data (or last known good data) and then mutes the analog circuit.
Compared with existing DAC technology, the PCM510xA devices offer up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs. (from traditional 100-kHz OBN measurements to 3 MHz).
The PCM510xA devices accept industry-standard audio data formats with 16- to 32-bit data. Sample rates up to 384 kHz are supported.
Sampling frequency is symbolized by fS. Full scale is symbolized by FS. Sample time as a unit is symbolized by tS.
The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM510xA on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK polarity for left/right is given by the format selected.
CONTROL MODE | FORMAT | DATA BITS | MAX LRCK FREQUENCY [fS] | SCK RATE [x fS] | BCK RATE [x fS] |
---|---|---|---|---|---|
Hardware Control | I2S/LJ | 32, 24, 20, 16 | Up to 192 kHz | 128 – 3072 (≤50MHz) | 64, 48, 32 |
384 kHz | 64, 128 | 64, 48, 32 |
The PCM510xA requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed.
If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and BCK is completed.
The PCM510xA supports industry-standard audio data formats, including standard I2S and left-justified. Data formats are selected using the FMT (pin 16), Low for I2S, and High for Left-justified. All formats require binary twos-complement, MSB-first audio data; up to 32-bit audio data is accepted.
The PCM510xA has a zero-data detect function. When the device detects continuous zero data, it enters a full analog mute condition. The PCM510xA counts zero data over 1024 LRCKs (21ms @ 48kHz) before setting analog mute.
In Hardware mode, the device uses default values. By default, Both L-ch and R-ch have to be zero data for zero data detection to begin the muting process etc.
An external digital host controls the PCM510xA soft mute function by driving the XSMT pin with a specific minimum rise time (tr) and fall time (tf) for soft mute and soft un-mute. The PCM510xA requires tr and tf times of less than 20ns. In the majority of applications, this is no problem, however, traces with high capacitance may have issues.
When the XSMT pin is shifted from high to low (3.3 V to 0 V), a soft digital attenuation ramp begins. –1-dB attenuation is then applied every sample time from 0 dBFS to –∞. The soft attenuation ramp takes 104 samples.
When the XSMT pin is shifted from low to high (0 V to 3.3 V), a soft digital “un-mute” is started. 1-dB gain steps are applied every sample time from –∞ to 0 dBFS. The un-mute takes 104 samples.
In systems where XSMT is not required, it can be directly connected to AVDD.
The PCM510xA provides two types of interpolation filter. Users can select which filter to use by using the FLT pin (pin 11).
FLT Pin | Description |
0 | FIR normal x8/x4/x2/x1 interpolation filters |
1 | IIR low-latency x8/x4/x2/x1 interpolation filters |
The normal x8 / x4 / x2 / x1(bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz.
Parameter | Condition | Value (Typ) | Value (Max) | Units |
Filter gain pass band | 0 ……. 0.45fS | ±0.02 | dB | |
Filter gain stop band | 0.55fS ….. 7.455fS | –60 | dB | |
Filter group delay | 22tS | s |
The normal x4 / x2 / x1 (bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz.
Parameter | Condition | Value (Typ) | Value (Max) | Units |
Filter gain pass band | 0 ……. 0.45fS | ±0.02 | dB | |
Filter gain stop band | 0.55fS ….. 7.455fS | –60 | dB | |
Filter group delay | 22tS | s |
Parameter | Condition | Value (Typ) | Value (Max) | Units |
Filter gain pass band | 0 ……. 0.45fS | ±0.02 | dB | |
Filter gain stop band | 0.55fS ….. 7.455fS | –60 | dB | |
Filter group delay | 22tS | s |
The low-latency x8 / x4 / x2 / x1 (bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz.
Parameter | Condition | Value (Typ) | Units |
Filter gain pass band | 0 ……. 0.45fS | ±0.0001 | dB |
Filter gain stop band | 0.55fS ….. 7.455fS | –52 | dB |
Filter group delay | 3.5tS | s |
Parameter | Condition | Value (Typ) | Units |
Filter gain pass band | 0 ……. 0.45fS | ±0.0001 | dB |
Filter gain stop band | 0.55fS ….. 3.455fS | –52 | dB |
Filter group delay | 3.5tS | s |
Parameter | Condition | Value (Typ) | Units |
Filter gain pass band | 0 ……. 0.45fS | ±0.0001 | dB |
Filter gain stop band | 0.55fS ….. 1.455fS | –52 | dB |
Filter group delay | 3.5tS | s |
space
The PCM510xA devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the serial audio interface in one form or another.
The data flows at the sample rate (fS). Once the data is brought into the serial audio interface, it gets processed, interpolated and modulated all the way to 128 × fS before arriving at the current segments for the final digital to analog conversion.
The serial audio interface typically has 4 connections SCK (system master clock), BCK (bit clock), LRCK (left right word clock) and DIN (data). The device has an internal PLL that is used to take either SCK or BCK and create the higher rate clocks required by the interpolating processor and the DAC clock. This allows the device to operate with or without an external SCK.
The PCM510xA requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input and supports up to 50 MHz. The PCM510xA system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz - 44.1 kHz - 48 kHz), (88.2kHz - 96kHz), (176.4 kHz - 192 kHz), and 384 kHz with ±4% tolerance are supported. Values in the parentheses are grouped when detected, e.g. 88.2kHZ and 96kHz are detected as "double rate," 32kHz, 44.1kHz and 48kHz will be detected as "single rate".
The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 10 shows examples of system clock frequencies for common audio sampling rates.
SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in software mode, available only in the PCM512x, PCM514x, and PCM5242 devices, by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for example, using 12 MHz to generate 44.1 kHz [LRCK] and 2.8224 MHz [BCK]).
Sampling Frequency | System Clock Frequency (fSCK) (MHz) | |||||||||||
64 fS | 128 fS | 192 fS | 256 fS | 384 fS | 512 fS | 768 fS | 1024 fS | 1152 fS | 1536 fS | 2048 fS | 3072 fS | |
8 kHz | –(1) | 1.024(2) | 1.536(2) | 2.048 | 3.072 | 4.096 | 6.144 | 8.192 | 9.216 | 12.288 | 16.384 | 24.576 |
16 kHz | –(1) | 2.048(2) | 3.072(2) | 4.096 | 6.144 | 8.192 | 12.288 | 16.384 | 18.432 | 24.576 | 36.864 | 49.152 |
32 kHz | –(1) | 4.096(2) | 6.144(2) | 8.192 | 12.288 | 16.384 | 24.576 | 32.768 | 36.864 | 49.152 | –(1) | –(1) |
44.1 kHz | –(1) | 5.6488(2) | 8.4672(2) | 11.2896 | 16.9344 | 22.5792 | 33.8688 | 45.1584 | –(1) | –(1) | –(1) | –(1) |
48 kHz | –(1) | 6.144(2) | 9.216(2) | 12.288 | 18.432 | 24.576 | 36.864 | 49.152 | –(1) | –(1) | –(1) | –(1) |
88.2 kHz | –(1) | 11.2896(2) | 16.9344 | 22.5792 | 33.8688 | 45.1584 | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) |
96 kHz | –(1) | 12.288(2) | 18.432 | 24.576 | 36.864 | 49.152 | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) |
176.4 kHz | –(1) | 22.579 | 33.8688 | 45.1584 | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) |
192 kHz | –(1) | 24.576 | 36.864 | 49.152 | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) |
384 kHz | 24.576 | 49.152 | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) | –(1) |
The system clock PLL mode allows designers to use a simple 3-wire I2S audio source. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagnetic interference.
The internal PLL is disabled as soon as an external SCK is supplied.
The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock.Table 11 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK.
BCK (fS) | ||
Sample f (kHz) | 32 | 64 |
8 | – | – |
16 | – | 1.024 |
32 | 1.024 | 2.048 |
44.1 | 1.4112 | 2.8224 |
48 | 1.536 | 3.072 |
96 | 3.072 | 6.144 |
192 | 6.144 | 12.288 |
384 | 12.288 | 24.576 |
As discussed in Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM), the internal PLL of a PCM510xA device supplies a SCK if an external SCK is not present at powerup.
Interpolation-filter options are controlled by the FLT pin. See Table 3.
De-emphasis control for 44.1-kHz fS is controlled by the DEMP pin. See Pin Configuration and Functions.
Audio format is selected by the FMT pin. See Pin Configuration and Functions.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The PCM510xA devices are powered through the following pins:
NAME | USAGE / DESCRIPTION |
---|---|
AVDD | Analog voltage supply; must be 3.3 V. This powers all analog circuitry that the DAC runs on. |
DVDD | Digital voltage supply. This is used as the I/O voltage control and the input to the onchip LDO. |
CPVDD | Charge Pump Voltage Supply - must be 3.3 V |
LDOO | Output from the onchip LDO. Should be used with a 0.1-µF decoupling cap. Can be driven (used as power input) with a 1.8-V supply to bypass the onchip LDO for lower power consumption. |
AGND | Analog ground |
DGND | Digital ground |
Under certain conditions, the PCM510xA devices can exhibit some pop on power down. Pops are caused by a device not having enough time to detect power loss and start the muting process.
The PCM510xA devices have two auto-mute functions to mute the device upon power loss (intentional or unintentional).
XSMT = 0
When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog mute. This process takes 150 sample times (ts) + 0.2 ms.
Because this mute time is mainly dominated by the sampling frequency, systems sampling at 192 kHz will mute much faster than a 48-kHz system.
Clock Error Detect
When clock error is detected on the incoming data clock, the PCM510xA devices switch to an internal oscillator, and continue to the drive the output, while attenuating the data from the last known value. Once this process is complete, the PCM510xA outputs are hard muted to ground.
These auto-muting processes can be manipulated by system designs to mute before power loss in the following ways:
Many systems use a low-noise regulator to provide an AVDD 3.3-V supply for the DAC. The XSMT Pin can take advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the output before the entire SMPS discharges. Figure 38 shows how to configure such a system to use the XSMT pin. The XSMT pin can also be used in parallel with a GPIO pin from the system microcontroller/DSP or power supply.
NOTE
External Power Sense Undervoltage Protection Mode is supported only when DVDD = 3.3 V.
The XSMT pin can also be used to monitor a system voltage, such as the 24-VDC LCD TV backlight, or 12-VDC system supply using a voltage divider created with two resistors. (See Figure 39 )
If XSMT is moved from "1" to "0" in 20 ns or less, then the device will interpret it as a digital controlled request to mute. It will perform a soft mute, then move to standby.
A timing diagram to show this is shown in Figure 40.
NOTE
The XSMT input pin voltage range is from –0.3 V to DVDD+0.3 V. The ratio of external resistors must produce a voltage within this input range. Any increase in power supply (such as power supply positive noise or ripple) can pull the XSMT pin higher than DVDD+0.3 V.
For example, if the PCM510xA is monitoring a 12-V input, and dividing the voltage by 4, then the voltage at XSMT during ideal power supply conditions is 3.3 V. A voltage spike higher than 14.4 V causes a voltage greater than 3.6 V (DVDD+0.3) on the XSMT pin, potentially damaging the device.
Providing the divider is set appropriately, any DC voltage can be monitored.
The trigger voltage values for the soft mute and hard mute are shown in Table 13. The range of values will vary from device to device, but typical thresholds are shown. XSMT should be set up to nominally be 3.3 V along with DVDD, but derived from a higher system power supply rail.
MIN | TYP | MAX | |
---|---|---|---|
Soft Mute Threshold Voltage | 2.0 V | 2.2 V | 0.9×DVDD |
Hard Mute Threshold Voltage | 0.1×DVDD | 0.9 V | 1.2 V |
Power-On Reset, DVDD 3.3-V Supply
The PCM510xA includes a power-on reset function shown in Figure 41. With VDD > 2.8 V, the power-on reset function is enabled. After the initialization period, the PCM510xA is set to its default reset state. Analog output will begin ramping after valid data has been passing through the device for the given group delay given by the digital interpolation filter selected.
Power-On Reset, DVDD 1.8-V Supply
The PCM510xA includes a power-on reset function shown in Figure 42 operating at DVDD = 1.8 V. With AVDD greater than approximately 2.8 V, CPVDD greater than approximately 2.8 V, and DVDD greater than approximately 1.5 V, the power-on reset function is enabled. After the initialization period, the PCM510xA is set to its default reset state.
The internal digital core of the PCM510xA devices run from a 1.8-V supply. This can be generated by the internal LDO, or by an external 1.8-V supply.
DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V required by the digital core.
For systems that require 3.3 V I/O support, but lower power consumption, DVDD should be connected to 3.3 V and LDOO can be connected to an external 1.8-V source. Doing so will disable the onchip LDO.
When setting I/O voltage to be 1.8 V, both DVDD and LDOO must be provided with an external 1.8-V supply.
The PCM510xA devices offer two power-save modes: standby and power-down.
When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510xA device automatically enters standby mode. The DAC and line driver are also powered down.
When BCK and LRCK remain at a low level for more than 1 second, the PCM510xA device automatically enters powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition to those disabled in standby mode.
When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA device, or if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup sequence automatically.