SLLS301R APRIL   1998  – January 2016 SN65LVDS050 , SN65LVDS051 , SN65LVDS179 , SN65LVDS180

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Device Electrical Characteristics
    6. 8.6  Driver Electrical Characteristics
    7. 8.7  Receiver Electrical Characteristics
    8. 8.8  Driver Switching Characteristics
    9. 8.9  Receiver Switching Characteristics
    10. 8.10 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Driver
    2. 9.2 Receiver
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Driver Offset
      2. 10.3.2 5-V Input Tolerance
      3. 10.3.3 NC Pins
      4. 10.3.4 Driver Equivalent Schematics
      5. 10.3.5 Receiver Features
        1. 10.3.5.1 Receiver Output States
        2. 10.3.5.2 Receiver Open-Circuit Fail-Safe
        3. 10.3.5.3 Receiver Power-On Reset
        4. 10.3.5.4 Common-Mode Range vs Supply Voltage
        5. 10.3.5.5 General Purpose Comparator
        6. 10.3.5.6 Receiver Equivalent Schematics
    4. 10.4 Device Functional Modes
      1. 10.4.1 Function Tables
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Equipment
        2. 11.2.2.2 Driver Supply Voltage
        3. 11.2.2.3 Driver Bypass Capacitance
        4. 11.2.2.4 Driver Output Voltage
        5. 11.2.2.5 Interconnecting Media
        6. 11.2.2.6 PCB Transmission Lines
        7. 11.2.2.7 Termination Resistor
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Microstrip vs. Stripline Topologies
      2. 13.1.2 Dielectric Type and Board Construction
      3. 13.1.3 Recommended Stack Layout
      4. 13.1.4 Separation Between Traces
      5. 13.1.5 Crosstalk and Ground Bounce Minimization
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Third-Party Products Disclaimer
      2. 14.1.2 Other LVDS Products
    2. 14.2 Documentation Support
      1. 14.2.1 Related Information
    3. 14.3 Related Links
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|14
  • PW|14
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard
  • Full-Duplex Signaling Rates up to 150 Mbps (See Table 1)
  • Bus-Pin ESD Exceeds 12 kV
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100-Ω Load
  • Propagation Delay Times
    • Driver: 1.7 ns Typical
    • Receiver: 3.7 ns Typical
  • Power Dissipation at 200 MHz
    • Driver: 25 mW Typical
    • Receiver: 60 mW Typical
  • LVTTL Input Levels Are 5-V Tolerant
  • Receiver Maintains High Input Impedance With VCC < 1.5 V
  • Receiver Has Open-Circuit Fail Safe

2 Applications

  • Wireless Infrastructure
  • Telecom Infrastructure
  • Printer

3 Description

The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 devices are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps (see Table 1). The TIA/EIA-644 standard-compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-Ω load and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN65LVDS179 SOIC (8) 4.90 mm × 3.91 mm
VSSOP (8) 3.00 mm × 3.00 mm
SN65LVDS180 SOIC (14) 8.65 mm × 3.91 mm
TSSOP (14) 5.00 mm × 4.40 mm
SN65LVDS050 SOIC (16) 9.90 mm × 3.91 mm
TSSOP (16) 5.00 mm × 4.40 mm
SN65LVDS051 SOIC (16) 9.90 mm × 3.91 mm
TSSOP (16) 5.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Equivalent Input and Output Schematic Diagrams

SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 iodia_lls301.gif