The TPS3808xxx family of microprocessor supervisory circuits monitors system voltages from 0.4 V to 5.0 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user-adjustable delay time after the SENSE voltage and manual reset (MR) return above the respective thresholds.
The TPS3808 uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be user-adjusted between 1.25 ms and 10 s by connecting the CT pin to an external capacitor. The TPS3808 has a very low typical quiescent current of 2.4 μA, so it is well-suited to battery-powered applications. It is available in a small SOT-23 package, and is fully specified over a temperature range of –55°C to +125°C (TJ).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS3808-EP | SOT (6) | 2.90 mm x 1.60 mm |
Changes from C Revision (September 2008) to D Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
RESET | 1 | O | RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pullup resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. |
GND | 2 | — | Ground |
MR | 3 | I | Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90kΩ pullup resistor. |
CT | 4 | I | Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open results in fixed delay times (see Switching Characteristics). Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See the Selecting the Reset Delay Time section for more information. |
SENSE | 5 | I | This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage VIT, then RESET is asserted. |
VDD | 6 | I | Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close to this pin. |