The TPS7A88 is a dual, low-noise (3.8 µVRMS), low-dropout (LDO) voltage regulator capable of sourcing 1 A per channel with only 200 mV of maximum dropout.
The TPS7A88 provides the flexibility of two independent LDOs and approximately 50% smaller solution size than two single-channel LDOs. Each output is adjustable with external resistors from 0.8 V to 5.0 V. The TPS7A88 wide input-voltage range supports operation as low as 1.4 V and up to 6.5 V.
With 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce in-rush current, the TPS7A88 is ideal for powering sensitive analog low-voltage devices [such as voltage-controlled oscillators (VCOs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), high-end processors, and field-programmable gate arrays (FPGAs)].
The TPS7A88 is designed to power up noise-sensitive components such as those found in high-speed communication, video, medical, or test and measurement applications. The very low 4-µVRMS output noise and wideband PSRR (40 dB at 1 MHz) minimizes phase noise and clock jitter. These features maximize performance of clocking devices, ADCs, and DACs.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A88 | WQFN (20) | 4.00 mm × 4.00 mm |
PIN | DESCRIPTION | ||
---|---|---|---|
NAME | NO. | I/O | |
EN1 | 20 | I | Enable pin for each channel. These pins turn the regulator on and off. If VENx(1) ≥ VIH(ENx), the regulator is enabled. If VENx ≤ VIL(ENx), the regulator is disabled. The ENx pin must be connected to INx if the enable function is not used. |
EN2 | 6 | ||
FB1 | 16 | I | Feedback pin for each channel. These pins are the inputs to the control loop error amplifier and are used to set the output voltage of the device. |
FB2 | 10 | ||
GND | 3, 13 | — | Device GND. Connect both pins to the device thermal pad. |
IN1 | 1, 2 | I | Input pin for LDO1. A 10 µF or greater input capacitor is required to assure robust operation. |
IN2 | 4, 5 | Input pin for LDO2. A 10 µF or greater input capacitor is required to assure robust operation. | |
NR/SS1 | 19 | — | Noise reduction pin for each channel. Connect these pins to an external capacitor to bypass the noise generated by the internal band-gap reference. The capacitor reduces the output RMS noise to very low levels and sets the output ramp rate to limit inrush current. |
NR/SS2 | 7 | ||
OUT1 | 14, 15 | O | Regulated output 1. A 10 µF or greater capacitor must be connected from this pin to GND to assure stability. |
OUT2 | 11, 12 | Regulated output 2. A 10 µF or greater capacitor must be connected from this pin to GND to assure stability. | |
PG1 | 17 | O | Open-drain power-good indicator pins for the LDO1 and LDO2 output voltages. A 10-kΩ to 100-kΩ external pullup resistor is required. These pins can be left floating or connected to GND if not used. |
PG2 | 9 | ||
SS_CTRL1 | 18 | I | Soft-start control pin for each channel. Connect these pins either to GND or INx to allow normal or fast charging of the NR/SSx capacitor. If a CNR/SSx capacitor is not used, SS_CTRLx must be connected to GND to avoid output overshoot. |
SS_CTRL2 | 8 | ||
Thermal pad | — | Connect the thermal pad to the printed circuit board (PCB) ground plane. |