TPS62125 3V～17V、300mA降圧型コンバータ、可変イネーブル・スレッショルドおよびヒステリシス付き
- JAJSBR8E March 2012 – May 2017 TPS62125
  
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TPS62125 3V～17V、300mA降圧型コンバータ、可変イネーブル・スレッショルドおよびヒステリシス付き

このリソースの元の言語は英語です。翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

3V～17Vの広い入力電圧範囲
入力電源電圧スーパーバイザ(SVS)、スレッショルドおよびヒステリシスを設定可能、標準静止電流6µA
広い出力電圧範囲: 1.2V～10V
静止電流: 13μA (標準値)
シャットダウン時電流: 350nA (標準値)
シームレスなパワーセーブ・モード移行
DCS-Control™方式
低い出力リップル電圧
最大1MHzのスイッチング周波数
広いV_INおよびV_OUT範囲にわたって最高の効率を維持
TPS62160/70とピン互換
100%デューティ・サイクル・モード
パワー・グッド用オープン・ドレイン出力
出力放電機能
小型の2mm×2mm、8ピンWSONパッケージ

2 アプリケーション

組み込み処理
4セルのアルカリ、または1～4セルのリチウムイオン・バッテリ駆動のアプリケーション
9V～15Vのスタンバイ電源
環境発電
インバータ(負のV_OUT)

3 概要

TPS62125デバイスは、高効率の同期整流降圧型コンバータで、最大300mAの出力電流を供給する低消費電力、および超低消費電力のアプリケーション用に最適化されています。入力電圧範囲が3V～17Vと広く、4セルのアルカリ、および1～4セルのリチウムイオン・バッテリの直列構成、および9V～15Vの電源で動作するアプリケーションをサポートします。このデバイスには、高精度の低消費電力イネーブル・コンパレータが内蔵されており、入力電源電圧スーパーバイザ(SVS)として使用することで、システム固有の電源オンおよび電源オフの要件に対応できます。イネーブル・コンパレータはわずか6μAの静止電流しか消費せず、正確な1.2V（標準値）のスレッショルドおよび可変ヒステリシスを備えています。これらの機能により、このコンバータはソーラー・パネルや電流ループなどの高インピーダンスのソースから電力を供給されるストレージ・コンデンサからエネルギーを抽出し、電源レールを生成できます。このコンバータは、DCS-Control方式によりパワー・セーブ・モードで動作し、負荷電流範囲の全体にわたって最高の効率を維持します。コンバータは、軽負荷時にはパルス周波数変調(PFM)モードで動作し、負荷電流の大きいときにはシームレスかつ自動的にパルス幅変調(PWM)モードへ移行します。この DCS-Control™方式はPFMモードで出力リップル電圧が低くなるよう最適化されており、出力ノイズを最小に抑え、非常に優れたAC負荷レギュレーションを行えます。出力電圧がレギュレート状態になると、オープン・ドレインのパワー・グッド出力により通知されます。

製品情報⁽¹⁾

型番	パッケージ	本体サイズ(公称)
TPS62125	WSON (8)	2.00mm×2.00mm

利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。

代表的なアプリケーションの回路図

効率と入力電圧との関係

TPS62125 effvs_VIN_3.3V_VLF302515_15uH.gif

4 改訂履歴

Changes from D Revision (July 2015) to E Revision

Added SW node AC abs max ratings Go

Changes from C Revision (December 2013) to D Revision

Added 「ピン構成および機能」セクション、「ESD定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションGo

5 Pin Configuration and Functions

DSG Package

8-Pin WSON

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
EN	3	IN	Input pin for the enable comparator. Pulling this pin to GND turns the device into shutdown mode. The DC/DC converter is enabled once the rising voltage on this pin trips the enable comparator threshold, V_{TH EN ON} of typ. 1.2 V. The DC/DC converter is turned off once a falling voltage on this pin trips the threshold, V_{TH EN OFF} of typ. 1.15 V. The comparator threshold can be increased by connecting an external resistor to pin EN_hys. See also application section. This pin must be terminated.
EN_hys	4	OUT	Enable hysteresis open-drain output. This pin is pulled to GND when the voltage on the EN pin is below the comparator threshold V_{TH EN ON} of typ. 1.2 V and the comparator has not yet tripped. The pin is high impedance once the enable comparator has tripped and the voltage at the pin EN is above the threshold V_{TH EN ON}. The pin is pulled to GND once the falling voltage on the EN pin trips the threshold V_{TH EN OFF}(1.15 V typical). This pin can be used to increase the hysteresis of the enable comparator. If not used, tie this pin to GND, or leave it open.
FB	5	IN	This is the feedback pin for the regulator. An external resistor divider network connected to this pin sets the output voltage. In case of fixed output voltage option, the resistor divider is integrated and the pin need to be connected directly to the output voltage.
GND	1	PWR	GND supply pin.
PG	8	OUT	Open drain power good output. This pin is internally pulled to GND when the device is disabled or the output voltage is below the PG threshold. The pin is floating when the output voltage is in regulation and above the PG threshold. For power good indication, the pin can be connected via a pull up resistor to a voltage rail up to 10 . The pin can sink a current up to 0.4 mA and maintain the specified high/low voltage levels. It can be used to discharge the output capacitor with up to 10 mA. In this case the current into the pin must be limited with an appropriate pull up resistor. More details can be found in the application section. If not used, leave the pin open, or connect to GND.
SW	7	OUT	This is the switch pin and is connected to the internal MOSFET switches. Connect the inductor to this pin. Do not tie this pin to VIN, VOUT or GND.
VIN	2	PWR	V_IN power supply pin.
VOS	6	IN	This is the output voltage sense pin for the DCS-Control circuitry. This pin must be connected to the output voltage of the DC/DC converter.
Exposed Thermal PAD	–	–	This pad must be connected to GND.

6 Specifications

6.1 Absolute Maximum Ratings

⁽¹⁾

		MIN	MAX	UNIT
Pin voltage⁽²⁾	VIN	–0.3	20	V
	SW (DC)	–0.3	V_IN + 0.3V	V
	SW (AC, less than 10ns)⁽³⁾	-3.0	23.5	V
	EN	–0.3	V_IN + 0.3	V
	FB	–0.3	3.6	V
	VOS, PG	–0.3	12	V
	EN_hys	–0.3	7	V
Power good sink current	I_PG		10	mA
EN_hys sink current	I_{EN_hys}		3	mA
Maximum operating junction temperature, T_J		–40	125	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal GND.

(3) While switching

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	MAX	UNIT
V_IN	Supply voltage		3	17	V
	Output current capability	3 V ≤ V_IN < 6 V		200	mA
	Output current capability	6 V ≤ V_IN ≤ 17 V		300	mA
T_A	Operating ambient temperature ⁽¹⁾ (Unless Otherwise Noted)		–40	85	°C
T_J	Operating junction temperature,		–40	125	°C

(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T_A(max)) is dependent on the maximum operating junction temperature (T_J(max)) and the maximum power dissipation of the device in the application (P_D(max)); for more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS62125	UNIT
		DSG (WSON)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	65.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	93.3	°C/W
R_θJB	Junction-to-board thermal resistance	30.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	47.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	7.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

T_A = –40°C to 85°C, typical values are at T_A = 25°C (unless otherwise noted), V_IN = 12 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
V_IN	Input voltage range⁽¹⁾		3		17	V
V_OUT	Output voltage range		1.2		10	V
I_Q	Quiescent current	I_OUT = 0 mA, device not switching, EN = V_IN, regulator sleeps		13	23	µA
		I_OUT = 0 mA, device switching, V_IN = 7.2 V, V_OUT = 1.2 V, L = 22 µH		14		µA
		V_IN = 5 V, EN = 1.1 V, enable comparator active, device DC/DC converter off		6	11	µA
I_Active	Active mode current consumption	V_IN = 5 V = V_OUT, T_A = 25°C, high-side MOSFET switch fully turned on (100% mode)		230	275	µA
I_SD	Shutdown current⁽²⁾	Enable comparator off, EN < 0.4 V, V_OUT = SW = 0 V, V_IN = 5 V		0.35	2.4	µA
V_UVLO	Undervoltage lockout threshold	Falling V_IN		2.8	2.85	V
V_UVLO	Undervoltage lockout threshold	Rising V_IN		2.9	2.95	V
ENABLE COMPARATOR THRESHOLD AND HYSTERESIS (EN, EN_hys)
V_{TH EN ON}	EN pin threshold rising edge	3 V ≤ V≤ 17 V	1.16	1.20	1.24	V
V_{TH EN OFF}	EN pin threshold falling edge		1.12	1.15	1.19	V
V_{TH EN Hys}	EN pin hysteresis _IN			50		mV
I_{IN EN}	Input bias current into EN pin	EN = 1.3 V		0	50	nA
V_{EN_hyst}	EN_hys pin output low	I_{EN_hyst} = 1 mA, EN = 1.1 V			0.4	V
I_{IN EN_hyst}	Input bias current into EN_hyst pin	EN_hyst = 1.3 V		0	50	nA
POWER SWITCH
R_DS(ON)	High-side MOSFET ON-resistance	V_IN = 3 V, I = 100 mA		2.4	4	Ω
	High-side MOSFET ON-resistance	V_IN = 12 V, I = 100 mA		1.5	2.6
	Low-side MOSFET ON-resistance	V_IN = 3 V, I = 100 mA		0.75	1.3
	Low-side MOSFET ON-resistance	V_IN = 12 V, I = 100 mA		0.6	1
I_LIMF	Switch current limit high-side MOSFET	V_IN = 12 V	600	750	900	mA
T_SD	Thermal shutdown	Increasing junction temperature		150		°C
T_SD	Thermal shutdown hysteresis	Decreasing junction temperature		20		°C
OUTPUT
t_ONmin	Minimum ON-time	V_IN = 5 V, V_OUT = 2.5 V		500		ns
t_OFFmin	Minimum OFF-time	V_IN = 5 V		60		ns
V_{REF_FB}	Internal reference voltage of error amplifier			0.808		V
V_FB	Feedback voltage accuracy	Referred to internal reference (V_{REF_FB})	–2.5%	0%	2.5%
	Feedback voltage line regulation	I_OUT = 100 mA, 5 V ≤ V_IN ≤ 17 V, V_OUT = 3.3 V⁽³⁾		–0.05		%/V
	Feedback voltage load regulation	V_OUT = 3.3 V; I_OUT = 1 mA to 300 mA, V_IN = 12 V⁽³⁾		–0.004		%/mA
I_{IN_FB}	Input bias current into FB pin	V_FB = 0.8 V		0	50	nA
t_Start	Regulator start-up time	Time from EN high to device starts switching, V_IN = 5 V		50		µs
t_Ramp	Output voltage ramp time	Time to ramp up V_OUT = 1.8 V, no load		200		µs
I_{LK_SW}	Leakage current into SW pin⁽⁴⁾	VOS = V_IN = V_SW = 1.8 V, EN = GND, device in shutdown mode		1.8	2.85	µA
I_{IN_VOS}	Bias current into VOS pin			0	50	nA
POWER GOOD OUTPUT (PG)
V_{TH_PG}	Power good threshold voltage	Rising V_FB feedback voltage	93%	95%	97%
V_{TH_PG}	Power good threshold voltage	Falling V_FB feedback voltage	87%	90%	93%
V_OL	PG pin output low voltage	Current into PG pin I_PG= 0.4 mA			0.3	V
V_OH	PG pin output high voltage	Open drain output, external pullup resistor			10	V
I_{IN_PG}	Bias current into PG pin	V_(PG) = 3 V, EN = 1.3 V, FB = 0.85 V		0	50	nA

(1) The part is functional down to the falling UVLO (Undervoltage Lockout) threshold

(2) Current into VIN pin

(3) V_OUT = 3.3 V, L = 15 µH, C_OUT = 10 µF

(4) An internal resistor divider network with typ. 1 MΩ total resistance is connected between SW pin and GND.

6.6 Typical Characteristics

Figure 1. Shutdown Current vs. Input Voltage

Figure 3. Quiescent Current vs. EN Voltage, Rising V_EN

Figure 5. EN Comparator Thresholds vs. Input Voltage

Figure 7. R_DSON Low-Side Switch (Rectifier)

Figure 2. Quiescent Current vs. Input Voltage

Figure 4. Quiescent Current vs. V_EN Voltage, Falling V_EN

Figure 6. R_DSON High-Side Switch

7 Detailed Description

7.1 Overview

The TPS62125 high-efficiency synchronous switch mode buck converter includes TI's DCS-Control (Direct Control with Seamless Transition into Power-Save Mode), an advanced regulation topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of DCS-Control are excellent AC load regulation and transient response, low-output ripple voltage and a seamless transition between PFM and PWM mode operation.

DCS-Control includes an AC loop which senses the output voltage (VOS pin) and directly feeds the information to a fast comparator stage. This comparator sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. In order to achieve accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The DCS-Control topology supports pulse width modulation (PWM) mode for medium and high load conditions and a power-save mode at light loads. During PWM mode, it operates in continuous conduction. The switch frequency is up to 1 MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter seamless enters power-save mode to maintain high efficiency down to very light loads. In power-save mode the switching frequency varies linearly with the load current. Because DCS-Control supports both operation modes within one single building block, the transition from PWM to power-save mode is seamless without effects on the output voltage. The TPS62125 offers both excellent DC voltage and superior load transient regulation, combined with very low-output voltage ripple, minimizing interference with RF circuits.

At high load currents the converter operates in quasi fixed frequency PWM mode operation and at light loads in pulse frequency modulation (PFM) mode to maintain highest efficiency over the full load current range. In PFM mode, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to achieve a quiescent current of typically 13 µA. During this time, the load current is supported by the output capacitor. The duration of the sleep period depends on the load current and the inductor peak current.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Undervoltage Lockout

In addition to the EN comparator, the device includes an under-voltage lockout circuit which prevents the device from misoperation at low input voltages. Both circuits are fed to an AND gate and prevents the converter from turning on the high-side MOSFET switch or low-side MOSFET under undefined conditions. The UVLO threshold is set to 2.9 V typical for rising V_IN and 2.8 V typical for falling V_IN. The hysteresis between rising and falling UVLO threshold ensures proper start-up. Fully functional operation is permitted for an input voltage down to the falling UVLO threshold level. The converter starts operation again once the input voltage trips the rising UVLO threshold level and the voltage at the EN pin trips V_{TH_EN_ON}.

7.3.2 Enable Comparator (EN / EN_hys)

The EN pin is connected to an on/shutdown detector (ON/SD) and an input of the enable comparator. With a voltage level of 0.4 V or less at the EN pin, the ON/SD detector turns the device into Shutdown mode and the quiescent current is reduced to typically 350 nA. In this mode the EN comparator as well the entire internal-control circuitry are switched off. A voltage level of typical 900 mV (rising) at the EN pin triggers the on/shutdown detector and activates the internal reference V_REF (typical 1.2 V), the EN comparator and the UVLO comparator. In applications with slow rising voltage levels at the EN pin, the quiescent current profile before this trip point needs to be considered, see Figure 3. Once the ON/SD detector has tripped, the quiescent current consumption of the device is typical 6 µA. The TPS62125 starts regulation once the voltage at the EN pin trips the threshold V_{EN_TH ON} (typical 1.2 V) and the input voltage is above the UVLO threshold. It enters softstart and ramps up the output voltage. For proper operation, the EN pin must be terminated and must not be left floating. The quiescent current consumption of the TPS62125 is typical 13 µA under no load condition (not switching). See Figure 1. The DC/DC regulator stops operation once the voltage on the EN pin falls below the threshold V_{EN_TH OFF} (typical 1.15 V) or the input voltage falls below UVLO threshold. The enable comparator features a built in hysteresis of typical 50 mV. This hysteresis can be increased with an external resistor connected to pin EN_hys.

7.3.3 Power Good Output and Output Discharge (PG)

The power good output (PG pin) is an open drain output. The circuit is active once the device is enabled. It is driven by an internal comparator connected to the FB pin voltage and an internal reference. The PG output provides a high level (open drain high impedance) once the feedback voltage exceeds typical 95% of its nominal value. The PG output is driven to low level once the FB pin voltage falls below typical 90% of its nominal value V_{REF_FB}. The PG output goes high (high impedance) with a delay of typically 2 µs. A pull up resistor is needed to generate a high level. The PG pin can be connected via a pull up resistors to a voltage up to 10 V. This pin can also be used to discharge the output capacitor. See section Application Information for more details.

The PG output is pulled low if the voltage on the EN pin falls below the threshold V_{EN_TH OFF}or the input voltage is below the undervoltage lockout threshold UVLO.

7.3.4 Thermal Shutdown

As soon as the junction temperature, T_J, exceeds 150°C (typical) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis.

7.4 Device Functional Modes

7.4.1 Pulse Width Modulation (PWM) Operation

The TPS62125 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal switching frequency of about 1 MHz. The frequency variation in PWM mode is controlled and depends on V_IN, V_OUT and the inductance. The device operates in PWM mode as long the output current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device enters power-save mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the inductor's ripple current.

7.4.2 Power-Save Mode

With decreasing load current, the TPS62125 transitions seamlessly from PWM mode to power-save mode once the inductor current becomes discontinuous. This ensures a high efficiency at light loads. In power-save mode the converter operates in pulse frequency modulation (PFM) mode and the switching frequency decreases linearly with the load current. DCS-Control features a small and predictable output voltage ripple in power-save mode. The transition between PWM mode and power-save mode occurs seamlessly in both directions.

The minimum ON-time T_ONmin for a single pulse can be estimated by:

Equation 1. TPS62125 EQ_TON1.gif

Therefore the peak inductor current in PFM mode is approximately:

Equation 2. TPS62125 EQ2_ILPF_lvsad5.gif

where

T_ON: High-side MOSFET switch on time [µs]
V_IN: Input voltage [V]
V_OUT: Output voltage [V]
L : Inductance [µH]
I_LPFMpeak : PFM inductor peak current [mA]

The transition from PFM mode to PWM mode operation and back occurs at a load current of approximately 0.5 x I_LPFMpeak.

The maximum switching frequency can be estimated by:

Equation 3. TPS62125 EQ_fswmax.gif

7.4.3 100% Duty Cycle Low Dropout Operation

The device increases the ON-time of the high-side MOSFET switch as the input voltage comes close to the output voltage in order to keep the output voltage in regulation. This reduces the switching frequency.

With further decreasing input voltage V_IN, the high-side MOSFET switch is turned on completely. In this case, the converter provides a low input-to-output voltage difference. This is particularly useful in applications with a widely variable supply voltage to achieve longest operation time by taking full advantage of the whole supply voltage span.

The minimum input voltage to maintain output voltage regulation depends on the load current and output voltage, and can be calculated as:

Equation 4. TPS62125 EQ_100_mode.gif

where

I_OUT: Output current
R_DS(ON)max: Maximum high-side switch R_DS(ON)
R_L: DC resistance of the inductor
V_OUTmin: Minimum output voltage the load can accept

7.4.4 Soft-Start

The TPS62125 has an internal soft-start circuit which controls the ramp up of the output voltage and limits the inrush current during start-up. This limits input voltage drop.

The soft-start system generates a monotonic ramp up of the output voltage and reaches an output voltage of 1.8 V typical within 240 µs after the EN pin was pulled high. For higher output voltages, the ramp up time of the output voltage can be estimated with a ramp up slew rate of about 12 mV/us. TPS62125 is able to start into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value. In case the output voltage is higher than the nominal value, the device starts switching once the output has been discharged by an external load or leakage current to its nominal output voltage value.

During start-up the device can provide an output current of half of the high-side MOSFET switch current limit I_LIMF. Large output capacitors and high load currents may exceed the current capability of the device during start-up. In this case the start-up ramp of the output voltage will be slower.

7.4.5 Short-Circuit Protection

The TPS62125 integrates a high-side MOSFET switch current limit, I_LIMF, to protect the device against a short circuit. The current in the high-side MOSFET switch is monitored by a current limit comparator and once the current reaches the limit of I_LIMF , the high-side MOSFET switch is turned off and the low-side MOSFET switch is turned on to ramp down the inductor current. The high-side MOSFET switch is turned on again once the zero current comparator trips and the inductor current has become zero. In this case, the output current is limited to half of the high-side MOSFET switch current limit, 0.5 x I_LIMF, typ. 300mA.