LM25145 42V同期整流降圧コントローラは、高い入力電圧の電源、または高い過渡電圧が発生する入力レールからのレギュレーションを行うよう設計されており、外部のサージ抑制コンポーネントの必要性を最小限に抑えます。ハイサイド・スイッチの最小のオン時間は40nsで、大きな降圧率を使用できるため、24V公称入力から低電圧レールへの直接降圧変換が可能になり、システムの複雑性とソリューションのコストを下げることができます。LM25145は最低6Vの入力電圧ディップ時にも動作を継続でき、必要に応じてほぼ100%のデューティ・サイクルでも動作できるため、高性能の産業用制御、ロボティクス、データコム、RFパワー・アンプのアプリケーションに最適です。
強制PWM (FPWM)動作により周波数変動が排除され、EMIが最小化されます。また、ユーザー選択のダイオード・エミュレーション機能により軽負荷の状況で消費電力が抑えられます。サイクル単位の過電流保護は、ローサイドMOSFETの両端での電圧降下測定、またはオプションの電流センシング抵抗を使用して行われます。スイッチング周波数は最大1MHzまで設定可能で、外部クロック・ソースと同期できるため、ノイズに敏感なアプリケーションでビート周波数を排除できます。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
LM25145 | VQFN (20) | 3.50mm×4.50mm |
日付 | 改訂内容 | 注 |
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2017年6月 | * | 初版 |
SPACER
LM25145電圧モード・コントローラは、外部のハイサイドおよびローサイドNチャネル電力スイッチを、標準スレッショルドのMOSFETに適した、堅牢な7.5Vのゲート・ドライバで駆動します。適応型タイミングのゲート・ドライブと、ソース2.3A、シンク3.5Aの能力から、スイッチング遷移時にボディ・ダイオードの導通が最小化され、スイッチング損失が低減し、高い入力電圧と高周波数でMOSFETを駆動するときの特性が改善されます。LM25145はスイッチング・レギュレータの出力、または他の利用可能な電源で駆動できるため、さらに効率が向上します。
SYNCOUTでの、内部発振器に対して180°位相がずれたクロック出力は、カスケードまたはマルチチャネルの電源で入力コンデンサのリップル電流とEMIフィルタのサイズを減らすため理想的です。LM25145の追加機能として、構成可能なソフトスタート、フォルト報告および出力監視用のオープン・ドレインのパワー・グッド・モニタ、プリバイアス負荷への単調スタートアップ、VCCバイアス電源レギュレータおよびブートストラップ・ダイオードの搭載、外部電源のトラッキング、可変のライン低電圧誤動作防止(UVLO)を行うための高精度のヒステリシス付きイネーブル入力、Hiccupモードの過負荷保護、自動回復機能付きのサーマル・シャットダウン保護があります。
LM25145コントローラは3.5mm×4.5mmの熱的に強化された20ピンのVQFNパッケージで供給され、高電圧ピンには追加のスペースを設け、ウェッタブル・フランクを採用してハンダ接合部フィレットの光学検査を容易に行えます。
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | EN/UVLO | I | Enable input and undervoltage lockout programming pin. If the EN/UVLO voltage is below 0.4 V, the controller is in the shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 0.4 V and less than 1.2 V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and no switching at the HO and LO outputs. If the EN/UVLO voltage is above 1.2 V, the SS/TRK pin is allowed to ramp and pulse-width modulated gate drive signals are delivered to the HO and LO pins. A 10-μA current source is enabled when EN/UVLO exceeds 1.2 V and flows through the external UVLO resistor divider to provide hysteresis. Hysteresis can be adjusted by varying the resistance of the external divider. |
2 | RT | I | Oscillator frequency adjust pin. The internal oscillator is programmed with a single resistor between RT and the AGND. The recommended maximum oscillator frequency is 1 MHz. An RT pin resistor is required even when using the SYNCIN pin to synchronize to an external clock. |
3 | SS/TRK | I | Soft-start and voltage tracking pin. An external capacitor and an internal 10-μA current source set the ramp rate of the error amplifier reference during start-up. When the SS/TRK pin voltage is less than 0.8 V, the SS/TRK voltage controls the noninverting input of the error amp. When the SS/TRK voltage exceeds 0.8 V, the amplifier is controlled by the internal 0.8-V reference. SS/TRK is discharged to ground during standby and fault conditions. After start-up, the SS/TRK voltage is clamped 115 mV above the FB pin voltage. If FB falls due to a load fault, SS/TRK is discharged to a level 115 mV above FB to provide a controlled recovery when the fault is removed. Voltage tracking can be implemented by connecting a low impedance reference between 0 V and 0.8 V to the SS/TRK pin. The 10-µA SS/TRK charging current flows into the reference and produces a voltage error if the impedance is not low. Connect a minimum capacitance from SS/TRK to AGND of 2.2 nF. |
4 | COMP | O | Low impedance output of the internal error amplifier. The loop compensation network should be connected between the COMP pin and the FB pin. |
5 | FB | I | Feedback connection to the inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is nominally 0.8 V. |
6 | AGND | P | Analog ground. Return for the internal 0.8-V voltage reference and analog circuits. |
7 | SYNCOUT | O | Synchronization output. Logic output that provides a clock signal that is 180° out-of-phase with the high-side FET gate drive. Connect SYNCOUT of the master LM25145 to the SYNCIN pin of a second LM25145 to operate two controllers at the same frequency with 180° interleaved high-side FET switch turnon transitions. Note that the SYNCOUT pin does not provide 180° interleaving when the controller is operating from an external clock that is different from the free-running frequency set by the RT resistor. |
8 | SYNCIN | I | Dual function pin for providing an optional clock input and for enabling diode emulation by the low-side MOSFET. Connecting a clock signal to the SYNCIN pin synchronizes switching to the external clock. Diode emulation by the low-side MOSFET is disabled when the controller is synchronized to an external clock, and negative inductor current can flow in the low-side MOSFET with light loads. A continuous logic low state at the SYNCIN pin enables diode emulation to prevent reverse current flow in the inductor. Diode emulation results in DCM operation at light loads, which improves efficiency. A logic high state at the SYNCIN pin disables diode emulation producing forced-PWM (FPWM) operation. During soft-start when SYNCIN is high or a clock signal is present, the LM25145 operates in diode emulation mode until the output is in regulation, then gradually increases the SW zero-cross threshold, resulting in a gradual transition from DCM to FPWM. |
9 | NC | — | No electrical connection. |
10 | PGOOD | O | Power Good indicator. This pin is an open-drain output. A high state indicates that the voltage at the FB pin is within a specified tolerance window centered at 0.8 V. |
11 | ILIM | I | Current limit adjust and current sense comparator input. A current sourced from the ILIM pin through an external resistor programs the threshold voltage for valley current limiting. The opposite end of the threshold adjust resistor can be connected to either the drain of the low-side MOSFET for RDS(on) sensing or to a current sense resistor connected to the source of the low-side FET. |
12 | PGND | P | Power ground return pin for the low-side MOSFET gate driver. Connect directly to the source of the low-side MOSFET or the ground side of a shunt resistor. |
13 | LO | P | Low-side MOSFET gate drive output. Connect to the gate of the low-side synchronous rectifier FET through a short, low inductance path. |
14 | VCC | O | Output of the 7.5-V bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as close to the controller as possible. Controller bias can be supplied from an external supply that is greater than the internal VCC regulation voltage. Use caution when applying external bias to ensure that the applied voltage is not greater than the minimum VIN voltage and does not exceed the VCC pin maximum operating rating, see Recommended Operating Conditions. |
15 | EP | — | Pin internally connected to exposed pad of the package. Electrically isolated. |
16 | NC | — | No electrical connection. |
17 | BST | O | Bootstrap supply for the high-side gate driver. Connect to the bootstrap capacitor. The bootstrap capacitor supplies current to the high-side FET gate and should be placed as close to controller as possible. If an external bootstrap diode is used to reduce the time required to charge the bootstrap capacitor, connect the cathode of the diode to the BST pin and anode to VCC. |
18 | HO | P | High-side MOSFET gate drive output. Connect to the gate of the high-side MOSFET through a short, low inductance path. |
19 | SW | P | Switching node of the buck controller. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET using short, low inductance paths. |
20 | VIN | P | Supply voltage input for the VCC LDO regulator. |
— | EP | — | Exposed pad of the package. Electrically isolated. Solder to the system ground plane to reduce thermal resistance. |
100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins and terminals that are easily viewed. It is therefore difficult to determine visually whether or not the package is successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve the issue of side-lead wetting of leadless packaging. The LM25145 is assembled using a 20-pin VQFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs.