JAJSNI4
December 2021
DAC11001B
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
6.7
Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
6.8
Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
6.9
Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
6.10
Timing Diagrams
6.11
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Digital-to-Analog Converter Architecture
7.3.2
External Reference
7.3.3
Output Buffers
7.3.4
Internal Power-On Reset (POR)
7.3.5
Temperature Drift and Calibration
7.3.6
DAC Output Deglitch Circuit
7.4
Device Functional Modes
7.4.1
Fast-Settling Mode and THD
7.4.2
DAC Update Rate Mode
7.5
Programming
7.5.1
Daisy-Chain Operation
7.5.2
CLR Pin Functionality and Software Clear
7.5.3
Output Update (Synchronous and Asynchronous)
7.5.3.1
Synchronous Update
7.5.3.2
Asynchronous Update
7.5.4
Software Reset Mode
7.6
Register Map
7.6.1
NOP Register (address = 00h) [reset = 0x000000h for bits [23:0]]
7.6.2
DAC-DATA Register (address = 01h) [reset = 0x000000h for bits [23:0]]
7.6.3
CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
7.6.4
DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
7.6.5
TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
7.6.6
STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
7.6.7
CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Source Measure Unit (SMU)
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.2.2
High-Precision Control Loop
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Curves
8.2.3
Arbitrary Waveform Generation (AWG)
8.2.3.1
Design Requirements
8.2.3.2
Detailed Design Procedure
8.2.3.3
Application Curves
8.3
System Examples
8.3.1
Interfacing to a Processor
8.3.2
Interfacing to a Low-Jitter LDAC Source
8.3.3
Embedded Resistor Configurations
8.3.3.1
Minimizing Bias Current Mismatch
8.3.3.2
2x Gain Configuration
8.3.3.3
Generating Negative Reference
8.4
What to Do and What Not to Do
8.4.1
What to Do
8.4.2
What Not to Do
8.5
Initialization Set Up
9
Power Supply Recommendations
9.1
Power-Supply Sequencing
10
Layout
10.1
Layout Guidelines
10.1.1
PCB Assembly Effects on Precision
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Development Support
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
サポート・リソース
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
1
特長
20 ビット単調性:1LSB の DNL (最大)
積分直線性:1LSB の INL (最大)
低いノイズ:7nV/√
Hz
コードに依存せず低グリッチ:1nV-s
非常に優れた THD:
–118dB (f
OUT
= 20kHz、f
DAC
= 1MHz)
高速セトリング:1μs
フレキシブルな出力範囲:V
REFPF
~V
REFNF
高精度の内蔵帰還抵抗
50MHz、4 線式の SPI 互換インターフェイス
読み戻し
デイジー・チェーン
温度範囲:–40℃~+125℃
パッケージ:48 ピン LQFP