DLPU040C October   2016  – July 2024 DLP650LNIR , DLPC410

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Overview
      1. 1.2.1 The DLP Discovery 4100 Development Platform
      2. 1.2.2 DLP Discovery 4100 Development Platform Photo
  6. 2Hardware
    1. 2.1 Key Components
      1. 2.1.1  Xilinx Virtex 5 APPSFPGA
      2. 2.1.2  DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      3. 2.1.3  DLPA200 - DMD Micromirror Driver
      4. 2.1.4  DLPR410 - Configuration PROM for DLPC410 Controller
      5. 2.1.5  APPSFPGA Flash Configuration PROM
      6. 2.1.6  DMD Connectors
      7. 2.1.7  USB Controller
      8. 2.1.8  50MHz Oscillator
      9. 2.1.9  DDR2 SODIMM Connector
      10. 2.1.10 Connectors
        1. 2.1.10.1 JTAG Header H1
        2. 2.1.10.2 Mictor Connectors
        3. 2.1.10.3 GPIO Connectors
      11. 2.1.11 Battery
      12. 2.1.12 Power Supplies
        1. 2.1.12.1 J12 Power Connector
        2. 2.1.12.2 J18 Power Connector
        3. 2.1.12.3 REG. 0.9V
        4. 2.1.12.4 REG. 1.0V
        5. 2.1.12.5 REG. 1.8V
        6. 2.1.12.6 REG. 2.5V
        7. 2.1.12.7 REG. 3.3V
        8. 2.1.12.8 REG. 12V
    2. 2.2 Hardware Overview and Setup
      1. 2.2.1 Getting Started
      2. 2.2.2 User Connectors and I/O
        1. 2.2.2.1  J12 Input Power Connector
        2. 2.2.2.2  J18 Input Power Connector
        3. 2.2.2.3  J1 USB Connector Pinout
        4. 2.2.2.4  J3 USB GPIO
        5. 2.2.2.5  J6 GPIO_A Connector
        6. 2.2.2.6  J8 DLPC410 Mictor Connector
        7. 2.2.2.7  J9 USB/APPSFPGA Mictor Connector
        8. 2.2.2.8  J13 DMD Flex 1 Connector
        9. 2.2.2.9  J14 DMD Flex 2 Connector
        10. 2.2.2.10 J15 - DDR2 SODIMM Connector
        11. 2.2.2.11 J16, J17 EXP Connectors
        12. 2.2.2.12 H1 Xilinx FPGA JTAG Header
      3. 2.2.3 Configuration Jumpers
        1. 2.2.3.1 J2 – EXP Voltage Select
        2. 2.2.3.2 J4 – APPSFPGA Revision Select
        3. 2.2.3.3 J5 – Shared USB Signal Enable/Disable
        4. 2.2.3.4 J7 – USB EEPROM Programming Header
        5. 2.2.3.5 J10 – DLPA200 B Output Enable
      4. 2.2.4 Switches
        1. 2.2.4.1 SW1 - APPSFPGA Functional Switches
        2. 2.2.4.2 SW2 - APPSFPGA Reset
        3. 2.2.4.3 SW3 - DMD Power Float (Park)
        4. 2.2.4.4 SW4 - Input Power On/Off
      5. 2.2.5 Power and Status LEDs
        1. 2.2.5.1 D1 – USB Connection Indicator
        2. 2.2.5.2 D2 and D16 – APPSFPGA Done
        3. 2.2.5.3 D3 and D17 – DLPC410 Done
        4. 2.2.5.4 D9 – DDC_LED0
        5. 2.2.5.5 D10 – DDC_LED1
        6. 2.2.5.6 D11 – VLED0
        7. 2.2.5.7 D12 – VLED1
      6. 2.2.6 Test Points
  7. 3Software
    1. 3.1 Overview
      1. 3.1.1 Software Overview
        1. 3.1.1.1 DMD Image Control
        2. 3.1.1.2 Image Commands
    2. 3.2 DLP Discovery 4100 Operation
      1. 3.2.1 Quick Start Guide on Operation
    3. 3.3 Graphical User Interface
      1. 3.3.1 Menu Bar
        1. 3.3.1.1 File Menu
        2. 3.3.1.2 View Menu
        3. 3.3.1.3 DMD Menu
        4. 3.3.1.4 Execution Menu
        5. 3.3.1.5 Test Patterns Menu
        6. 3.3.1.6 Help Menu
      2. 3.3.2 Toolbar
        1. 3.3.2.1 File Menu Buttons
        2. 3.3.2.2 Run, Run Once, Loop Break, Step and Stop Controls
        3. 3.3.2.3 Set Start and End Buttons
        4. 3.3.2.4 Help Button
      3. 3.3.3 Script Commands Window
        1. 3.3.3.1 Load Tab
        2. 3.3.3.2 Reset Tab
        3. 3.3.3.3 Clear Tab
        4. 3.3.3.4 Float Tab
        5. 3.3.3.5 Control Tab
      4. 3.3.4 Status Window
      5. 3.3.5 Script Window
        1. 3.3.5.1 Inserting Commands
        2. 3.3.5.2 Moving Commands
        3. 3.3.5.3 Deleting Commands
    4. 3.4 Script and Status Operations
      1. 3.4.1 Saving Scripts and Statuses
        1. 3.4.1.1 Saving a Script
        2. 3.4.1.2 Saving a Status
      2. 3.4.2 Printing Scripts and Statuses
        1. 3.4.2.1 Printing a Script
        2. 3.4.2.2 Printing a Status
      3. 3.4.3 Opening Scripts and Statuses
      4. 3.4.4 Creating New Scripts and Statuses
        1. 3.4.4.1 Creating a New Script
        2. 3.4.4.2 Creating a New Status
    5. 3.5 DLPC410 Control Window
    6. 3.6 Test Patterns Window
    7. 3.7 About Box
    8. 3.8 Links
  8. 4Hardware Design Files
  9. 5Additional Information
    1. 5.1 Trademarks
    2. 5.2 Abbreviations and Acronyms
    3. 5.3 Notational Conventions
      1. 5.3.1 Information About Cautions and Warnings
  10. 6Related Documentation
  11. 7Revision History

2.2.2.8 J13 DMD Flex 1 Connector

Connector J13 provides control and data signals to the DMD Flex 1 connector. This connector is used for connection to all DMD types.

Table 2-8 J13 DMD Flex Connector 1
Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name
1A GND 1B 3.3V 1C 3.3V
2C GND 2A DDC_DOUT_A13_DPP 2B DDC_DOUT_A13_DPN
3A GND 3B DDC_DOUT_A11_DPP 3C DDC_DOUT_A11_DPN
4C GND 4A DDC_DOUT_A9_DPP 4B DDC_DOUT_A9_DPN
5A GND 5B DDC_DCLKOUT_A_DPP 5C DDC_DCLKOUT_A_DPN
6C GND 6A DDC_DOUT_A7_DPP 6B DDC_DOUT_A7_DPP
7A GND 7B DDC_DOUT_A5_DPP 7C DDC_DOUT_A5_DPN
8C GND 8A DDC_DOUT_A3_DPP 8B DDC_DOUT_A3_DPN
9A GND 9B DDC_DOUT_A1_DPP 9C DDC_DOUT_A1_DPN
10C GND 10A DAD_A_SCPDO 10B DAD_A_SCPCLK
11A GND 11B DMDSPARE1 11C DMD_A_SCPEN
12C GND 12A MBRST1_15 12B MBRST1_14
13A GND 13B DMD_VCC2 13C DMD_VCC2
14C GND 14A MBRST1_10 14B MBRST1_6
15A GND 15B MBRST1_9 15C MBRST1_7
16C GND 16A MBRST1_13 16B MBRST1_12
17A GND 17B DDC_DOUT_B1_DPP 17C DDC_DOUT_B1_DPN
18C GND 18A DDC_DOUT_B3_DPP 18B DDC_DOUT_B3_DPN
19A GND 19B DDC_DOUT_B5_DPP 19C DDC_DOUT_B5_DPN
20C GND 20A DDC_DOUT_B7_DPP 20B DDC_DOUT_B7_DPN
21A GND 21B DDC_DCLKOUT_B_DPP 21C DDC_DCLKOUT_B_DPN
22C GND 22A DDC_DOUT_B9_DPP 22B DDC_DOUT_B9_DPN
23A GND 23B DDC_DOUT_B11_DPP 23C DDC_DOUT_B11_DPN
24C GND 24A DDC_DOUT_B13_DPP 24B DDC_DOUT_B13_DPN
25A GND 25B DDC_DOUT_B15_DPP 25C DDC_DOUT_B15_DPN
1D GND 1E DDC_DOUT_A15_DPP 1F DDC_DOUT_A15_DPN
2F GND 2D DDC_DOUT_A14_DPP 2E DDC_DOUT_A14_DPN
3D GND 3E DDC_DOUT_A12_DPP 3F DDC_DOUT_A12_DPN
4F GND 4D DDC_DOUT_A10_DPP 4E DDC_DOUT_A10_DPN
5D GND 5E DDC_DOUT_A8_DPP 5F DDC_DOUT_A8_DPN
6F GND 6D DDC_SCTRL_A_DPP 6E DDC_SCTRL_A_DPN
7D GND 7E DDC_DOUT_A6_DPP 7F DDC_DOUT_A6_DPN
8F GND 8D DDC_DOUT_A4_DPP 8E DDC_DOUT_A4_DPN
9D GND 9E DDC_DOUT_A2_DPP 9F DDC_DOUT_A2_DPN
10F GND 10D DDC_DOUT_A0_DPP 10E DDC_DOUT_A0_DPN
11D GND 11E SCPDI 11F DMD_A_RESET
12F GND 12D DMDSPARE0 12E MBRST1_11
13D GND 13E MBRST1_5 13F MBRST1_4
14F GND 14D MBRST1_0 14E MBRST1_3
15D GND 15E MBRST1_2 15F MBRST1_8
16F GND 16D DDC_DOUT_B0_DPP 16E DDC_DOUT_B0_DPN
17D GND 17E DDC_DOUT_B2_DPP 17F DDC_DOUT_B2_DPN
18F GND 18D DDC_DOUT_B4_DPP 18E DDC_DOUT_B4_DPN
19D GND 19E DDC_DOUT_B6_DPP 19F DDC_DOUT_B6_DPN
20F GND 20D DDC_SCTRL_B_DPP 20E DDC_SCTRL_B_DPP
21D GND 21E DDC_DOUT_B8_DPP 21F DDC_DOUT_B8_DPN
22F GND 22D DDC_DOUT_B10_DPP 22E DDC_DOUT_B10_DPN
23D GND 23E DDC_DOUT_B12_DPP 23F DDC_DOUT_B12_DPN
24F GND 24D DDC_DOUT_B14_DPP 24E DDC_DOUT_B14_DPN
25D GND 25E 3.3V 25F 3.3V