DLPU040C October   2016  – July 2024 DLP650LNIR , DLPC410

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Overview
      1. 1.2.1 The DLP Discovery 4100 Development Platform
      2. 1.2.2 DLP Discovery 4100 Development Platform Photo
  6. 2Hardware
    1. 2.1 Key Components
      1. 2.1.1  Xilinx Virtex 5 APPSFPGA
      2. 2.1.2  DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      3. 2.1.3  DLPA200 - DMD Micromirror Driver
      4. 2.1.4  DLPR410 - Configuration PROM for DLPC410 Controller
      5. 2.1.5  APPSFPGA Flash Configuration PROM
      6. 2.1.6  DMD Connectors
      7. 2.1.7  USB Controller
      8. 2.1.8  50MHz Oscillator
      9. 2.1.9  DDR2 SODIMM Connector
      10. 2.1.10 Connectors
        1. 2.1.10.1 JTAG Header H1
        2. 2.1.10.2 Mictor Connectors
        3. 2.1.10.3 GPIO Connectors
      11. 2.1.11 Battery
      12. 2.1.12 Power Supplies
        1. 2.1.12.1 J12 Power Connector
        2. 2.1.12.2 J18 Power Connector
        3. 2.1.12.3 REG. 0.9V
        4. 2.1.12.4 REG. 1.0V
        5. 2.1.12.5 REG. 1.8V
        6. 2.1.12.6 REG. 2.5V
        7. 2.1.12.7 REG. 3.3V
        8. 2.1.12.8 REG. 12V
    2. 2.2 Hardware Overview and Setup
      1. 2.2.1 Getting Started
      2. 2.2.2 User Connectors and I/O
        1. 2.2.2.1  J12 Input Power Connector
        2. 2.2.2.2  J18 Input Power Connector
        3. 2.2.2.3  J1 USB Connector Pinout
        4. 2.2.2.4  J3 USB GPIO
        5. 2.2.2.5  J6 GPIO_A Connector
        6. 2.2.2.6  J8 DLPC410 Mictor Connector
        7. 2.2.2.7  J9 USB/APPSFPGA Mictor Connector
        8. 2.2.2.8  J13 DMD Flex 1 Connector
        9. 2.2.2.9  J14 DMD Flex 2 Connector
        10. 2.2.2.10 J15 - DDR2 SODIMM Connector
        11. 2.2.2.11 J16, J17 EXP Connectors
        12. 2.2.2.12 H1 Xilinx FPGA JTAG Header
      3. 2.2.3 Configuration Jumpers
        1. 2.2.3.1 J2 – EXP Voltage Select
        2. 2.2.3.2 J4 – APPSFPGA Revision Select
        3. 2.2.3.3 J5 – Shared USB Signal Enable/Disable
        4. 2.2.3.4 J7 – USB EEPROM Programming Header
        5. 2.2.3.5 J10 – DLPA200 B Output Enable
      4. 2.2.4 Switches
        1. 2.2.4.1 SW1 - APPSFPGA Functional Switches
        2. 2.2.4.2 SW2 - APPSFPGA Reset
        3. 2.2.4.3 SW3 - DMD Power Float (Park)
        4. 2.2.4.4 SW4 - Input Power On/Off
      5. 2.2.5 Power and Status LEDs
        1. 2.2.5.1 D1 – USB Connection Indicator
        2. 2.2.5.2 D2 and D16 – APPSFPGA Done
        3. 2.2.5.3 D3 and D17 – DLPC410 Done
        4. 2.2.5.4 D9 – DDC_LED0
        5. 2.2.5.5 D10 – DDC_LED1
        6. 2.2.5.6 D11 – VLED0
        7. 2.2.5.7 D12 – VLED1
      6. 2.2.6 Test Points
  7. 3Software
    1. 3.1 Overview
      1. 3.1.1 Software Overview
        1. 3.1.1.1 DMD Image Control
        2. 3.1.1.2 Image Commands
    2. 3.2 DLP Discovery 4100 Operation
      1. 3.2.1 Quick Start Guide on Operation
    3. 3.3 Graphical User Interface
      1. 3.3.1 Menu Bar
        1. 3.3.1.1 File Menu
        2. 3.3.1.2 View Menu
        3. 3.3.1.3 DMD Menu
        4. 3.3.1.4 Execution Menu
        5. 3.3.1.5 Test Patterns Menu
        6. 3.3.1.6 Help Menu
      2. 3.3.2 Toolbar
        1. 3.3.2.1 File Menu Buttons
        2. 3.3.2.2 Run, Run Once, Loop Break, Step and Stop Controls
        3. 3.3.2.3 Set Start and End Buttons
        4. 3.3.2.4 Help Button
      3. 3.3.3 Script Commands Window
        1. 3.3.3.1 Load Tab
        2. 3.3.3.2 Reset Tab
        3. 3.3.3.3 Clear Tab
        4. 3.3.3.4 Float Tab
        5. 3.3.3.5 Control Tab
      4. 3.3.4 Status Window
      5. 3.3.5 Script Window
        1. 3.3.5.1 Inserting Commands
        2. 3.3.5.2 Moving Commands
        3. 3.3.5.3 Deleting Commands
    4. 3.4 Script and Status Operations
      1. 3.4.1 Saving Scripts and Statuses
        1. 3.4.1.1 Saving a Script
        2. 3.4.1.2 Saving a Status
      2. 3.4.2 Printing Scripts and Statuses
        1. 3.4.2.1 Printing a Script
        2. 3.4.2.2 Printing a Status
      3. 3.4.3 Opening Scripts and Statuses
      4. 3.4.4 Creating New Scripts and Statuses
        1. 3.4.4.1 Creating a New Script
        2. 3.4.4.2 Creating a New Status
    5. 3.5 DLPC410 Control Window
    6. 3.6 Test Patterns Window
    7. 3.7 About Box
    8. 3.8 Links
  8. 4Hardware Design Files
  9. 5Additional Information
    1. 5.1 Trademarks
    2. 5.2 Abbreviations and Acronyms
    3. 5.3 Notational Conventions
      1. 5.3.1 Information About Cautions and Warnings
  10. 6Related Documentation
  11. 7Revision History

2.2.2.11 J16, J17 EXP Connectors

J16 and J17 provide connections to APPSFPGA compatible with the Avnet EXP Bus Specification. J16 and J17 can also be used as high speed interface connectors for accessory boards. The D4100 controller board routes some of the single-ended signals as differential pairs to support a full 64 bit 2xLVDS data bus. This routing can interfere with the EXP single-ended signals as noted in the Table 3-11 and Table 3-13.

Table 2-11 J16 EXP-1 Connector
J16 Pin Number Single Ended Signal Name Differential Pair Name APPSFPGA Pin Number J16 Pin Number Single Ended Signal Name Differential Pair Name APPSFPGA Pin Number
1 EXP1_SE_IO_1 A33 2 EXP1_SE_IO_0 C34
3 EXP1_SE_IO_3 B32 4 EXP1_SE_IO_2 D32
7 EXP1_SE_IO_5 B33 8 EXP1_SE_IO_4 D34
9 EXP1_SE_IO_7 C32 10 EXP1_SE_IO_6 E34
13 EXP1_SE_IO_9 H32 14 EXP1_SE_IO_8 G32
15 EXP1_SE_IO_11 C33 16 EXP1_SE_IO_10 F33
19 EXP1_SE_IO_13(1) EXP1_DIFF_23_P K33 20 EXP1_SE_IO_12(1) EXP1_DIFF_22 G33
21 EXP1_SE_IO_15(1) EXP1_DIFF_23_N K32 22 EXP1_SE_IO_14(1) EXP1_DIFF_22 F34
25 EXP1_SE_IO_17(1) EXP1_DIFF_25_P P34 26 EXP1_SE_IO_16(1) EXP1_DIFF_24 H34
27 EXP1_SE_IO_19(1) EXP1_DIFF_25_N N34 28 EXP1_SE_IO_18(1) EXP1_DIFF_24 J34
31 EXP1_SE_IO_21(1) EXP1_DIFF_27_P N33 32 EXP1_SE_IO_20(1) EXP1_DIFF_26 L34
33 EXP1_SE_IO_23(1) EXP1_DIFF_27_N M33 34 EXP1_SE_IO_22(1) EXP1_DIFF_26 K34
37 EXP1_SE_IO_25(1) EXP1_DIFF_29_P L33 38 EXP1_SE_IO_24(1) EXP1_DIFF_28 J32
39 EXP1_SE_IO_27(1) EXP1_DIFF_29_N M32 40 EXP1_SE_IO_26(1) EXP1_DIFF_28 H33
41 EXP1_SE_IO_28 E32 42 EXP1_DIFF_CLK_IN_DPP H19
43 EXP1_SE_CLK_IN J20 44 EXP1_DIFF_CLK_IN_DPN H20
47 EXP1_SE_IO_29 E33 48 EXP1_SE_IO_30(1) EXP1_DIFF_30_P R33
49 EXP1_SE_CLK_OUT J21 50 EXP1_SE_IO_3(1) EXP1_DIFF_30_N R32
53 EXP1_DIFF_21_P P32 54 EXP1_DIFF_20_P AC32
55 EXP1_DIFF_21_N N32 56 EXP1_DIFF_20_N AB32
59 EXP1_SE_IO_32(1) EXP1_DIFF_31_P T33 60 EXP1_DIFF_18_P AF34
61 EXP1_SE_IO_33(1) EXP1_DIFF_31_N R34 62 EXP1_DIFF_18_N AE34
65 EXP1_DIFF_19_P AG32 66 EXP1_DIFF_16_P U33
67 EXP1_DIFF_19_N AH32 68 EXP1_DIFF_16_N T34
71 EXP1_DIFF_17_P AJ32 72 EXP1_DIFF_CLK_OUT_P U3
73 EXP1_DIFF_17_N AK32 74 EXP1_DIFF_CLK_OUT_N U2
77 EXP1_DIFF_15_P W34 78 EXP1_DIFF_14_P V33
79 EXP1_DIFF_15_N V34 80 EXP1_DIFF_14_N V32
81 EXP1_DIFF_13_P AA34 82 EXP1_DIFF_12_P AD32
83 EXP1_DIFF_13_N Y34 84 EXP1_DIFF_12_N AE32
87 EXP1_DIFF_11_P Y32 88 EXP1_DIFF_10_P AL34
89 EXP1_DIFF_11_N W32 90 EXP1_DIFF_10_N AL33
93 EXP1_DIFF_9_P AA33 94 EXP1_DIFF_8_P AK34
95 EXP1_DIFF_9_N Y33 96 EXP1_DIFF_8_N AK33
99 EXP1_DIFF_7_P AC33 100 EXP1_DIFF_6_P AF33
101 EXP1_DIFF_7_N AB33 102 EXP1_DIFF_6_N AE33
105 EXP1_DIFF_5_P AC34 106 EXP1_DIFF_4_P AH34
107 EXP1_DIFF_5_N AD34 108 EXP1_DIFF_4_N AJ34
111 EXP1_DIFF_3_P AM33 112 EXP1_DIFF_2_P AG33
113 EXP1_DIFF_3_N AM32 114 EXP1_DIFF_2_N AH33
117 EXP1_DIFF_1_P AN34 118 EXP1_DIFF_0_P AN32
119 EXP1_DIFF_1_N AN33 120 EXP1_DIFF_0_N AP32
(1) Single ended /IO with shared differential pairs; must only be slow switching signals or only one side of the pair be used.
Table 2-12 J16 EXP-1 Power and Ground Connections
J16 Pin Number Power Connection
5, 6, 11, 12, 17, 18, 23, 24, 29, 30, 35, 36 VCC_2P5V
45, 46, 41, 52, 57, 58, 63, 64, 69, 70, 75, 76, 121, 122, 124, 125, 126, 127, 128, 129, 130, 131, 132 Ground
85, 86, 91, 92, 97, 98, 103, 104, 109, 110, 115, 116 VCC_3P3V
Table 2-13 J17 EXP-2 Connector
J17 Pin Number Single Ended Signal Name Differential Pair Name APPSFPGA Pin Number J17 Pin Number Single Ended Signal Name Differential Pair Name APPSFPGA Pin Number
1 EXP2_SE_IO_1 D1 2 EXP2_SE_IO_0 B3
3 EXP2_SE_IO_3 D2 4 EXP2_SE_IO_2 B1
7 EXP2_SE_IO_5 J2 8 EXP2_SE_IO_4 B2
9 EXP2_SE_IO_7 J1 10 EXP2_SE_IO_6 A3
13 EXP9_SE_IO_9 K1 14 EXP2_SE_IO_8 C2
15 EXP2_SE_IO_11 K2 16 EXP2_SE_IO_10 C3
19 EXP2_SE_IO_13(1) EXP2_DIFF_23_P H2 20 EXP2_SE_IO_12(1) EXP2_DIFF_22 E2
21 EXP2_SE_IO_15(1) EXP2_DIFF_23_N H3 22 EXP2_SE_IO_14(1) EXP2_DIFF_22 E1
25 EXP2_SE_IO_17(1) EXP2_DIFF_25_P P2 26 EXP2_SE_IO_16(1) EXP2_DIFF_24 E3
27 EXP2_SE_IO_19(1) EXP2_DIFF_25_N R3 28 EXP2_SE_IO_18(1) EXP2_DIFF_24 F3
31 EXP2_SE_IO_21(1) EXP2_DIFF_27_P T1 32 EXP2_SE_IO_20(1) EXP2_DIFF_26 F1
33 EXP2_SE_IO_23(1) EXP2_DIFF_27_N R1 34 EXP2_SE_IO_22(1) EXP2_DIFF_26 G1
37 EXP2_SE_IO_25(1) EXP2_DIFF_29_P K3 38 EXP2_SE_IO_24(1) EXP2_DIFF_28 G3
39 EXP2_SE_IO_27(1) EXP2_DIFF_29_N L3 40 EXP2_SE_IO_26(1) EXP2_DIFF_28 G2
41 EXP2_SE_IO_28 Y2 42 EXP2_DIFF_CLK_IN_DPP H18
43 EXP2_SE_CLK_IN J16 44 EXP2_DIFF_CLK_IN_DPN J17
47 EXP2_SE_IO_29 Y3 48 EXP2_SE_IO_30(1) EXP2_DIFF_30_P N2
49 EXP2_SE_CLK_OUT J15 50 EXP2_SE_IO_31 EXP2_DIFF_30_N M2
53 EXP2_DIFF_21_P M3 54 EXP2_DIFF_20_P M1
55 EXP2_DIFF_21_N N3 56 EXP2_DIFF_20_N L1
59 EXP2_SE_IO_32(1) EXP2_DIFF_31_P P1 60 EXP2_DIFF_18_P V4
61 EXP2_SE_IO_33(1) EXP2_DIFF_31_N R2 62 EXP2_DIFF_18_N V3
65 EXP2_DIFF_19_P U3 66 EXP2_DIFF_16_P W1
67 EXP2_DIFF_19_N T3 68 EXP2_DIFF_16_N V2
71 EXP2_DIFF_17_P U1 72 EXP2_DIFF_CLK_OUT_P AC3
73 EXP2_DIFF_17_N U2 74 EXP2_DIFF_CLK_OUT_N AB2
77 EXP2_DIFF_15_P W2 78 EXP2_DIFF_14_P AB3
79 EXP2_DIFF_15_N Y1 80 EXP2_DIFF_14_N AA3
81 EXP2_DIFF_13_P AF1 82 EXP2_DIFF_12_P AG1
83 EXP2_DIFF_13_N AE1 84 EXP2_DIFF_12_N AG2
87 EXP2_DIFF_11_P AF3 88 EXP2_DIFF_10_P AE2
89 EXP2_DIFF_11_N AE3 90 EXP2_DIFF_10_N AD2
93 EXP2_DIFF_9_P AH2 94 EXP2_DIFF_8_P AB1
95 EXP2_DIFF_9_N AJ2 96 EXP2_DIFF_8_N AA1
99 EXP2_DIFF_7_P AK2 100 EXP2_DIFF_6_P AG3
101 EXP2_DIFF_7_N AK3 102 EXP2_DIFF_6_N AH3
105 EXP2_DIFF_5_P AJ1 106 EXP2_DIFF_4_P AC2
107 EXP2_DIFF_5_N AK1 108 EXP2_DIFF_4_N AD1
111 EXP2_DIFF_3_P AM3 112 EXP2_DIFF_2_P AN2
113 EXP2_DIFF_3_N AN3 114 EXP2_DIFF_2_N AP2
117 EXP2_DIFF_1_P AL1 118 EXP2_DIFF_0_P AM2
119 EXP2_DIFF_1_N AM1 120 EXP2_DIFF_0_N AL3
(1) Single ended /IO with shared differential pairs; must only be slow switching signals or only one side of the pair be used.
Table 2-14 J17 EXP-2 Power and Ground Connections
J17 Pin NumberPower Connection
5, 6, 11, 12, 17, 18, 23, 24, 29, 30, 35, 36VCC_2P5V
45, 46, 41, 52, 57, 58, 63, 64, 69, 70, 75, 76, 121, 122, 124, 125, 126, 127, 128, 129, 130, 131 ,132Ground
85, 86, 91, 92, 97, 98, 103, 104, 109, 110, 115, 116VCC_3P3V