DLPU106A March 2021 – October 2021 DLP3021-Q1
This page determines the default start-up conditions of select DMD controller registers. Certain registers enable read and write permissions during typical operation to allow settings to be changed after flash programming, while certain registers only allow read permissions after flash programming during typical operation. See the DLP3021-Q1 FPGA User's Guide (DLPU100) for details on each register.
Key settings to configure on this page include:
whether or not content should be displayed immediately after power-up.
the ready state default display content immediately after power-up.
the PWM and duty cycle of each LED driver, and the PWM enable state.