DLPU113A December 2021 – April 2022 DLP2021-Q1
In this architecture, video content is compressed and stored in external flash memory. Low speed SPI commands are sent from the MSP430 MCU in Local Host Control operating mode or FTDI interface in Host Mute operating mode to the DMD controller to indicate what image/video content to read from the external 2Gb flash memory. Storing the image/video content in memory removes the need for a high-speed video interface to the module which improves compatibility with typical vehicle infrastructures. It also decreases overall system size and cost by removing graphics generation and interfaces. The controller decompresses each bit plane of the video data (416 × 468 resolution) and displays them on the DMD in rapid succession to create the full video image at a frame rate of 25 Hz. A frame rate of 25 Hz is recommended due to memory constraints, but the DLP2021-Q1 can support a maximum frame rate of 60 Hz. Due to the diamond format of the DMD pixels, the output image has an effective resolution of 588× 330. The controller synchronizes the DMD bit plane data with the RGB enable timing for the LED color controller and driver circuit.