DLPU133 March   2024 DLPC964

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 2.1 Get Started
    2. 2.2 Features
    3. 2.3 Assumptions
    4. 2.4 Apps FPGA Hardware Target
  5. 2Apps FPGA Modules
    1. 3.1  Apps FPGA Block Diagram
    2. 3.2  BPG Module
    3. 3.3  BRG Module
      1. 3.3.1 Start Signal Logic
      2. 3.3.2 Delay Needed Logic
      3. 3.3.3 Blocks Sent/Loaded Logic
    4. 3.4  BRG_ST Module
    5. 3.5  PGEN Module
    6. 3.6  PGEN_MCTRL Module
    7. 3.7  PGEN_SCTRL Module
    8. 3.8  PGEN_PRM Module
    9. 3.9  PGEN_ADDR_ROM
    10. 3.10 HSSTOP Module
    11. 3.11 SSF Module
    12. 3.12 ENC Module
    13. 3.13 Xilinx IP
      1. 3.13.1 PGEN_SPBROM_v3
      2. 3.13.2 MAINPLL
      3. 3.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
      4. 3.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
    14. 3.14 Reference Documents
    15. 3.15 DLPC964 Apps FPGA IO
    16. 3.16 Key Definitions
  6. 3Functional Configuration
    1. 4.1 Blocks Enabled
    2. 4.2 Pattern Cycle Enable
      1. 4.2.1 North/South Flip
      2. 4.2.2 TPG Patterns
      3. 4.2.3 Pattern Mode
      4. 4.2.4 Switching Modes
      5. 4.2.5 Changing the BPG Patterns
  7. 4Appendix
    1. 5.1 Vivado Chipscope Captures
    2. 5.2 DLPC964 Apps Bitstream Loading
      1. 5.2.1 Loading Bitstream onto FPGA
      2. 5.2.2 Loading Bitstream onto Flash
    3. 5.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 5.3.1 Theory of Operation
      2. 5.3.2 Overview
      3. 5.3.3 Aurora 64B/66B TX Core and RTL Generation
        1. 5.3.3.1  Select Aurora 64B66B From IP Catalog
        2. 5.3.3.2  Configure Core Options
        3. 5.3.3.3  Lane Configurations
        4. 5.3.3.4  Shared Logic Options
        5. 5.3.3.5  Generate Example Design Files
        6. 5.3.3.6  RTL File List
        7. 5.3.3.7  Single Channel 3 Lanes Aurora Core RTL Wrapper
        8. 5.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
        9. 5.3.3.9  Block Start with Block Control Word
        10. 5.3.3.10 Block Complete with DMDLOAD_REQ
        11. 5.3.3.11 DMDLOAD_REQ Setup Time Requirement
        12. 5.3.3.12 Single Channel Transfer Mode
        13. 5.3.3.13 DMD Block Array Data Mapping
        14. 5.3.3.14 Xilinx IBERT
  8. 5Abbreviations and Acronyms
  9. 6Related Documentation from Texas Instruments

4.2.2 Loading Bitstream onto Flash

Follow the instructions below for loading the DLPC964 Apps binary onto the flash via a bitstream using Vivado Lab Solutions 2018.2.

Note: Click the link above to download Vivado Lab Solutions 2018.2. Once the webpage is loaded, find the archived 2018.2 folder and then navigate to the Vivado Lab Solutions 2018.2 downloadable link and download the installation.
Note: The bitstream is always loaded onto the FPGA upon power-up of the AMD EVM.
  1. Plug in the micro USB into the side of the AMD EVM and the other end into the computer running Vivado.
  2. Make sure to set SW11 to 00010 (1 = on, Position 1 → Position 5, left to right).
    GUID-20231007-SS0I-TBLM-NKPL-BLGJ48KQ5PCW-low.png Figure 4-9 FPGA Configuration Mode
  3. Set SW2 to 00000000 (1 = on, Position 1 → Position 8, left to right).
    GUID-20231009-SS0I-H83M-FVWC-LJ0CCVB9JBS9-low.png Figure 4-10 GPIO Dip Switches (VC707)
  4. Start Vivado Lab Studios 2018.2 on the computer.
  5. Select Open Hardware Manager from the main window.
  6. Click open target located in the top left of the hardware manager then Auto Connect.
    1. If the AMD EVM is the only FPGA plugged into the computer, then Vivado automatically connects to the AMD EVM. Otherwise, the process is slightly more involved.
  7. Right-click on the FPGA and select Add Configuration Memory Device.
  8. Find the Flash name mt28gu01gaax1e-bpi-x16 and click OK.
  9. Select OK again and select the configuration file (appstop.mcs).
    1. Make sure all other settings match.
  10. Once setup, click OK. The programming can take a few minutes.
  11. Once completed, power cycle the AMD EVM and the DLPC964 Apps Bitstream automatically loads onto the AMD EVM.