DLPU133 March   2024 DLPC964

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 2.1 Get Started
    2. 2.2 Features
    3. 2.3 Assumptions
    4. 2.4 Apps FPGA Hardware Target
  5. 2Apps FPGA Modules
    1. 3.1  Apps FPGA Block Diagram
    2. 3.2  BPG Module
    3. 3.3  BRG Module
      1. 3.3.1 Start Signal Logic
      2. 3.3.2 Delay Needed Logic
      3. 3.3.3 Blocks Sent/Loaded Logic
    4. 3.4  BRG_ST Module
    5. 3.5  PGEN Module
    6. 3.6  PGEN_MCTRL Module
    7. 3.7  PGEN_SCTRL Module
    8. 3.8  PGEN_PRM Module
    9. 3.9  PGEN_ADDR_ROM
    10. 3.10 HSSTOP Module
    11. 3.11 SSF Module
    12. 3.12 ENC Module
    13. 3.13 Xilinx IP
      1. 3.13.1 PGEN_SPBROM_v3
      2. 3.13.2 MAINPLL
      3. 3.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
      4. 3.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
    14. 3.14 Reference Documents
    15. 3.15 DLPC964 Apps FPGA IO
    16. 3.16 Key Definitions
  6. 3Functional Configuration
    1. 4.1 Blocks Enabled
    2. 4.2 Pattern Cycle Enable
      1. 4.2.1 North/South Flip
      2. 4.2.2 TPG Patterns
      3. 4.2.3 Pattern Mode
      4. 4.2.4 Switching Modes
      5. 4.2.5 Changing the BPG Patterns
  7. 4Appendix
    1. 5.1 Vivado Chipscope Captures
    2. 5.2 DLPC964 Apps Bitstream Loading
      1. 5.2.1 Loading Bitstream onto FPGA
      2. 5.2.2 Loading Bitstream onto Flash
    3. 5.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 5.3.1 Theory of Operation
      2. 5.3.2 Overview
      3. 5.3.3 Aurora 64B/66B TX Core and RTL Generation
        1. 5.3.3.1  Select Aurora 64B66B From IP Catalog
        2. 5.3.3.2  Configure Core Options
        3. 5.3.3.3  Lane Configurations
        4. 5.3.3.4  Shared Logic Options
        5. 5.3.3.5  Generate Example Design Files
        6. 5.3.3.6  RTL File List
        7. 5.3.3.7  Single Channel 3 Lanes Aurora Core RTL Wrapper
        8. 5.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
        9. 5.3.3.9  Block Start with Block Control Word
        10. 5.3.3.10 Block Complete with DMDLOAD_REQ
        11. 5.3.3.11 DMDLOAD_REQ Setup Time Requirement
        12. 5.3.3.12 Single Channel Transfer Mode
        13. 5.3.3.13 DMD Block Array Data Mapping
        14. 5.3.3.14 Xilinx IBERT
  8. 5Abbreviations and Acronyms
  9. 6Related Documentation from Texas Instruments

3.2.2 TPG Patterns

When Pattern Cycle is enabled, patterns 1-8 is cycled through the DLPC964 controller. Patterns 9-14 are not cycled through, but can be selected by the customer.

Table 3-1 TPG Patterns
Pattern Number Value Name Description
1 0x0 Full-on Full white background where all the mirrors on the DMD is in the on position.
2 0x1 Full-off Full black background where all the mirrors on the DMD is in the off position.
3 0x2 Checkerboard A black and white checkerboard pattern with squares 64 pixels long by 68 lines high. The height and width were chosen to be a repeatable 136 x 1024 image.
4 0x3 Single pixel grid with border A single pixel border surrounds every 136 x 1024 area with a grid pattern inscribed inside each one. The vertical lines are spaced 32 pixels apart and the horizontal lines are spaced 34 lines apart.
5 0x4 West to East Diagonal Lines Diagonal lines spanning west to east of each segment.
6 0x5 East to West Diagonal Lines Diagonal lines spanning east to west of each segment.
7 0x6 Horizontal Lines 16 line wide horizontal lines.
8 0x7 Vertical Lines 16 pixel wide vertical lines.
9 0x8 Load2 checkerboard DEBUG PATTERN

A black and white checkerboard pattern with squares 32 pixels by 34 line high. The pattern continues between lines 0-67. Lines 68-135 are all black. This is to easily show how the load2 operation works.
10 0x9 Dots 10 by 10 DEBUG PATTERN

Customer requested pattern where single white pixels are spaced 8 pixels evenly in the X and Y direction.
11 0xA Inverting Checkerboard DEBUG PATTERN

This is an inverted version of the checkerboard pattern (0x2). When the user selects this pattern (0xA), the pattern timer register causes the BPG to flip between this pattern and the original checkerboard pattern (0x2). This is to help with hinge memory issues and must be used whenever the light source is off.
12 0xB Random Noise Pattern DEBUG PATTERN

Randomized noise pattern for customer tilt angle testing.
13 0xC 1x1 Horizontal Lines DEBUG PATTERN

Every row alternates between black/white and can be used to check for issues with row loads.
14 0xD 1x1 Vertical Lines DEBUG PATTERN

Every column alternates between black/white and can be used to check for issues with data bus lines.
15 0xE Full on/off DEBUG PATTERN

Selecting this pattern causes the BPG to toggle between full-on (0x0) and full-off (0x1) patterns based on the pattern timer value.