DLPU133 March   2024 DLPC964

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 2.1 Get Started
    2. 2.2 Features
    3. 2.3 Assumptions
    4. 2.4 Apps FPGA Hardware Target
  5. 2Apps FPGA Modules
    1. 3.1  Apps FPGA Block Diagram
    2. 3.2  BPG Module
    3. 3.3  BRG Module
      1. 3.3.1 Start Signal Logic
      2. 3.3.2 Delay Needed Logic
      3. 3.3.3 Blocks Sent/Loaded Logic
    4. 3.4  BRG_ST Module
    5. 3.5  PGEN Module
    6. 3.6  PGEN_MCTRL Module
    7. 3.7  PGEN_SCTRL Module
    8. 3.8  PGEN_PRM Module
    9. 3.9  PGEN_ADDR_ROM
    10. 3.10 HSSTOP Module
    11. 3.11 SSF Module
    12. 3.12 ENC Module
    13. 3.13 Xilinx IP
      1. 3.13.1 PGEN_SPBROM_v3
      2. 3.13.2 MAINPLL
      3. 3.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
      4. 3.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
    14. 3.14 Reference Documents
    15. 3.15 DLPC964 Apps FPGA IO
    16. 3.16 Key Definitions
  6. 3Functional Configuration
    1. 4.1 Blocks Enabled
    2. 4.2 Pattern Cycle Enable
      1. 4.2.1 North/South Flip
      2. 4.2.2 TPG Patterns
      3. 4.2.3 Pattern Mode
      4. 4.2.4 Switching Modes
      5. 4.2.5 Changing the BPG Patterns
  7. 4Appendix
    1. 5.1 Vivado Chipscope Captures
    2. 5.2 DLPC964 Apps Bitstream Loading
      1. 5.2.1 Loading Bitstream onto FPGA
      2. 5.2.2 Loading Bitstream onto Flash
    3. 5.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 5.3.1 Theory of Operation
      2. 5.3.2 Overview
      3. 5.3.3 Aurora 64B/66B TX Core and RTL Generation
        1. 5.3.3.1  Select Aurora 64B66B From IP Catalog
        2. 5.3.3.2  Configure Core Options
        3. 5.3.3.3  Lane Configurations
        4. 5.3.3.4  Shared Logic Options
        5. 5.3.3.5  Generate Example Design Files
        6. 5.3.3.6  RTL File List
        7. 5.3.3.7  Single Channel 3 Lanes Aurora Core RTL Wrapper
        8. 5.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
        9. 5.3.3.9  Block Start with Block Control Word
        10. 5.3.3.10 Block Complete with DMDLOAD_REQ
        11. 5.3.3.11 DMDLOAD_REQ Setup Time Requirement
        12. 5.3.3.12 Single Channel Transfer Mode
        13. 5.3.3.13 DMD Block Array Data Mapping
        14. 5.3.3.14 Xilinx IBERT
  8. 5Abbreviations and Acronyms
  9. 6Related Documentation from Texas Instruments

3.2.5 Changing the BPG Patterns

Below are instructions to help users change the default patterns in the ROM for TPG selections.

  1. Go into the directory C:\Texas Instruments\DLPC964-Apps\docs\patterns and verify that the user has Python 2.6 (or greater) installed.
  2. Open the binary_to_coe.py file and read through the top comments. The patterns used in the DLPC964 Apps were generated using this script. Look at the bit_fnames list located near the top of the script.
    GUID-20231110-SS0I-BH5B-DBR6-DZ98PLNGLHFB-low.png
  3. The user can create a new .txt file and replace one of the names within the bit_fnames list.
    Note: Any patterns designated RTL defined pattern cannot be changed to a different pattern since the patterns are not read from the ROM.
    1. Instructions for creating a .txt file for the python script:
      1. The text file MUST have 1024 columns and 136 lines.
      2. Each character in the text file must either be a '1' or a '0'.
      3. Make sure the text file is in the same directory as the python script.
  4. Once the bit_fnames has been updated with the new text file name, run the python script. This creates a file called bpg_patterns.coe
  5. Open the Vivado project (either by unzipping the archived project in the build\project directory, or by running the run.tcl script).
    Note: Unzipping the project is faster but if desired, then the run.tcl script has instructions on how to run.
    GUID-20231110-SS0I-HHMR-FLRB-MHV8NP1PWXLC-low.png
  6. Once the project is open, in the Project Manager window, find the tab labeled IP sources and click.
    GUID-20231110-SS0I-G4NV-VJQV-ZZQCZ0S1N2LN-low.png
  7. Right-click on pgen_spbrom_v3 and select re-customize IP.
    GUID-20231110-SS0I-Z9KP-8ZXP-Q0RLXXWG4MVG-low.png
  8. Once the IP configuration tool is open, go to the options tab and the user sees a Memory Initialization section.
    GUID-20231110-SS0I-FPMB-NNWH-CZTBW9GPQJMW-low.png
  9. Click Browse and navigate to the location of the bpg_patterns.coe file created by the python script in step 4. Assuming there are no errors, click OK. In the next window, click Generate.
  10. The user now has reprogrammed the ROM in the DLPC964 Apps FPGA. Now, re-build the project.
  11. Once Xilinx finishes generating output products, click Generate Bitstream located on the left in the Flow Navigator. Click OK to any prompts and once Vivado finishes, the bitstream can be found inside the project_1\project_1.runs\impl_1\ directory.
    GUID-20231110-SS0I-F8QG-ZFHQ-RG4BGJGJLHFT-low.png