DLPU133 March   2024 DLPC964

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 2.1 Get Started
    2. 2.2 Features
    3. 2.3 Assumptions
    4. 2.4 Apps FPGA Hardware Target
  5. 2Apps FPGA Modules
    1. 3.1  Apps FPGA Block Diagram
    2. 3.2  BPG Module
    3. 3.3  BRG Module
      1. 3.3.1 Start Signal Logic
      2. 3.3.2 Delay Needed Logic
      3. 3.3.3 Blocks Sent/Loaded Logic
    4. 3.4  BRG_ST Module
    5. 3.5  PGEN Module
    6. 3.6  PGEN_MCTRL Module
    7. 3.7  PGEN_SCTRL Module
    8. 3.8  PGEN_PRM Module
    9. 3.9  PGEN_ADDR_ROM
    10. 3.10 HSSTOP Module
    11. 3.11 SSF Module
    12. 3.12 ENC Module
    13. 3.13 Xilinx IP
      1. 3.13.1 PGEN_SPBROM_v3
      2. 3.13.2 MAINPLL
      3. 3.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
      4. 3.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
    14. 3.14 Reference Documents
    15. 3.15 DLPC964 Apps FPGA IO
    16. 3.16 Key Definitions
  6. 3Functional Configuration
    1. 4.1 Blocks Enabled
    2. 4.2 Pattern Cycle Enable
      1. 4.2.1 North/South Flip
      2. 4.2.2 TPG Patterns
      3. 4.2.3 Pattern Mode
      4. 4.2.4 Switching Modes
      5. 4.2.5 Changing the BPG Patterns
  7. 4Appendix
    1. 5.1 Vivado Chipscope Captures
    2. 5.2 DLPC964 Apps Bitstream Loading
      1. 5.2.1 Loading Bitstream onto FPGA
      2. 5.2.2 Loading Bitstream onto Flash
    3. 5.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 5.3.1 Theory of Operation
      2. 5.3.2 Overview
      3. 5.3.3 Aurora 64B/66B TX Core and RTL Generation
        1. 5.3.3.1  Select Aurora 64B66B From IP Catalog
        2. 5.3.3.2  Configure Core Options
        3. 5.3.3.3  Lane Configurations
        4. 5.3.3.4  Shared Logic Options
        5. 5.3.3.5  Generate Example Design Files
        6. 5.3.3.6  RTL File List
        7. 5.3.3.7  Single Channel 3 Lanes Aurora Core RTL Wrapper
        8. 5.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
        9. 5.3.3.9  Block Start with Block Control Word
        10. 5.3.3.10 Block Complete with DMDLOAD_REQ
        11. 5.3.3.11 DMDLOAD_REQ Setup Time Requirement
        12. 5.3.3.12 Single Channel Transfer Mode
        13. 5.3.3.13 DMD Block Array Data Mapping
        14. 5.3.3.14 Xilinx IBERT
  8. 5Abbreviations and Acronyms
  9. 6Related Documentation from Texas Instruments

4.3.3.11 DMDLOAD_REQ Setup Time Requirement

Apps FPGA user logics can assert the DMDLOAD_REQ signal as soon as completing an Aurora block transfer as long as the signal is at least 300ns after sending the first data packet of that block. This setup time requirement is due to the 300ns transmit latency of the Aurora TX/RX channel paths, thus verifies the DLPC964 receives the DMDLOAD_REQ flag after the arrival of Aurora block data.

In most cases, this 300ns setup requirement is met naturally as a data block is large enough to verify over 300ns from the first valid data packet being sent to the last ones of a block when the Apps can assert the DMDLOAD_REQ signal. Cases of this 300ns setup window become critical is when Apps FPGA tries to send a small partial DMD block such as in Figure 4-21 showing an example of the Apps FPGA sending a total of 3 rows (Table 4-2 , ROW_LENGTH = 3) of a DMD partial block to DLPC964:

GUID-20231113-SS0I-NRLC-JJLB-JNSZHJ6KPVZ9-low.png Figure 4-21 DMDLOAD_REQ Setup Time for Three DMD Rows Load Operation
  1. Apps FPGA transmits a Block Control word to indicate the start of an Aurora block transfer.
  2. After sending three rows of data through the four Aurora data interface channels, the Apps FPGA waits for the 300ns setup time to expire before issues a DMDLOAD_REQ.
    Note: The 300ns is measured from the start of the first TVALID on the data interface.
  3. Apps FPGA asserts DMDLOAD_REQ once the setup time is meet.
  4. BLKLOADZ asserted by DLPC964 indicating DMD data load operation in progress.

For operations that do not require the data packet, such as block clear (Table 3, LOAD_TYPE = 001) and block set (Table 3, LOAD_TYPE = 010). This DMDLOAD_REQ of 300ns setup time is still required and measured from the Block Control word packet. Figure 4-22 is an example of a block set operation.

GUID-20231113-SS0I-0PPL-WPPN-DJJXPCHRXVM4-low.png Figure 4-22 DMDLOAD_REQ Setup Time For Block Set Operation
  1. Apps FPGA transmits a Block Control word packet to start a block set operation. Notice this operation does not require any block data as the four data interfaces stay idle (gtX_s_axi_tx_tvalid = ‘0’).
  2. Apps FPGA asserts DMDLOAD_REQ after the 300ns setup time. 300ns is measured from Block Control word as block set operation does not require Aurora data transfer.
  3. DLPC964 asserts BLKLOADZ indicating block set operation in progress.