DLPU133A March 2024 – February 2025 DLPC964
There are four copies of the secondary control module that are controlled by the primary control module. Each secondary is responsible for sending out the proper length data valid signal and to increment the ROM address. The data valid signal goes to the Aurora interface to mark the data being sent as valid. The Aurora interface can de-assert the ready signal at various times, so the secondary module must take this into account by holding the values and valid signal until the ready signal is re-asserted. The maximum ROM address is sent to the secondary module by the primary control module. The secondary module counts up to this value allowing the ROMs to send out lines up to the user-specified amount. Figure 2-7 depicts the main Secondary FSM where each state machine is defined as followed: