DLPU133 March   2024 DLPC964

1.   1
2.   Abstract
3.   Trademarks
4. 1Overview
   1. 2.1 Get Started
   2. 2.2 Features
   3. 2.3 Assumptions
   4. 2.4 Apps FPGA Hardware Target
5. 2Apps FPGA Modules
   1. 3.1  Apps FPGA Block Diagram
   2. 3.2  BPG Module
   3. 3.3  BRG Module
      1. 3.3.1 Start Signal Logic
      2. 3.3.2 Delay Needed Logic
      3. 3.3.3 Blocks Sent/Loaded Logic
   4. 3.4  BRG_ST Module
   5. 3.5  PGEN Module
   6. 3.6  PGEN_MCTRL Module
   7. 3.7  PGEN_SCTRL Module
   8. 3.8  PGEN_PRM Module
   9. 3.9  PGEN_ADDR_ROM
   10. 3.10 HSSTOP Module
   11. 3.11 SSF Module
   12. 3.12 ENC Module
   13. 3.13 Xilinx IP
       1. 3.13.1 PGEN_SPBROM_v3
       2. 3.13.2 MAINPLL
       3. 3.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
       4. 3.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
   14. 3.14 Reference Documents
   15. 3.15 DLPC964 Apps FPGA IO
   16. 3.16 Key Definitions
6. 3Functional Configuration
   1. 4.1 Blocks Enabled
   2. 4.2 Pattern Cycle Enable
      1. 4.2.1 North/South Flip
      2. 4.2.2 TPG Patterns
      3. 4.2.3 Pattern Mode
      4. 4.2.4 Switching Modes
      5. 4.2.5 Changing the BPG Patterns
7. 4Appendix
   1. 5.1 Vivado Chipscope Captures
   2. 5.2 DLPC964 Apps Bitstream Loading
      1. 5.2.1 Loading Bitstream onto FPGA
      2. 5.2.2 Loading Bitstream onto Flash
   3. 5.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 5.3.1 Theory of Operation
      2. 5.3.2 Overview
      3. 5.3.3 Aurora 64B/66B TX Core and RTL Generation
         1. 5.3.3.1  Select Aurora 64B66B From IP Catalog
         2. 5.3.3.2  Configure Core Options
         3. 5.3.3.3  Lane Configurations
         4. 5.3.3.4  Shared Logic Options
         5. 5.3.3.5  Generate Example Design Files
         6. 5.3.3.6  RTL File List
         7. 5.3.3.7  Single Channel 3 Lanes Aurora Core RTL Wrapper
         8. 5.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
         9. 5.3.3.9  Block Start with Block Control Word
         10. 5.3.3.10 Block Complete with DMDLOAD_REQ
         11. 5.3.3.11 DMDLOAD_REQ Setup Time Requirement
         12. 5.3.3.12 Single Channel Transfer Mode
         13. 5.3.3.13 DMD Block Array Data Mapping
         14. 5.3.3.14 Xilinx IBERT
8. 5Abbreviations and Acronyms
9. 6Related Documentation from Texas Instruments