SBAA275A June 2018 – March 2023 ADS1120 , ADS112C04 , ADS112U04 , ADS1147 , ADS1148 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1220 , ADS122C04 , ADS122U04 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS125H02 , ADS1260 , ADS1261 , ADS1262 , ADS1263
In this topology, two measurements are taken for lead resistance cancellation. In the first measurement, the ADC measures the voltage across the RTD and the resistance for lead 1 as driven by the single excitation current source. In the second measurement, the ADC measures the resistance for lead 3 as driven by the same excitation current source. This method assumes that the resistance in lead 1 and lead 3 are equal. By subtracting the second measurement from the first, the RTD resistance can be accurately measured, and the lead resistance cancelled.
The measurement circuit requires:
Starting with IDAC1 driving AIN0, the voltage at AIN1 and AIN2 can be calculated. For the first measurement:
Because current does not flow through lead 2, there is no RLEAD2 term in the measurement. For the second measurement, the ADC measures the voltage from AIN2 to AIN3.
VMEAS2 yields the measurement of the lead 3 resistance. Subtracting VMEAS2 from VMEAS1, the result is:
Assuming the resistance from lead 1 equals the resistance from lead 3, the result is:
For both VMEAS1 and VMEAS2, the reference resistor shunts IIDAC1 for a reference voltage of:
As with the previous examples, start the design with the expected usable range of the RTD. The reference resistor and IDAC current values are chosen to place the input voltage within the PGA range, while ensuring that the IDAC is operating within its compliance voltage. As in all ratiometric measurements, the reference resistor, RREF must be a precision resistor with high accuracy and low drift.
To verify that the design is within the PGA range of operation, start by calculating the voltages of AIN1 and AIN2 and the maximum differential input voltage. Assuming the lead resistances are small and can be ignored, Equation 41 and Equation 42 reduce to Equation 49 and Equation 50. Verify that VAIN1 and VAIN2 are within the input range of the PGA given the gain setting and supply voltage. Use the maximum RTD resistance based on the desired temperature measurement.
Additionally, verify the output voltage of the IDAC sources calculated from VAIN0 and VAIN3 are low enough from AVDD to be within the compliance voltage of the IDAC current source. Because the voltage for IDAC1 always be higher than that of IDAC2, it is sufficient to calculate the output voltage at VAIN0 to verify the IDAC compliance voltage. This calculation is already shown in Equation 49, because VAIN0 is the same potential as VAIN1.
The reference resistor, RREF must be a precision resistor with high accuracy and low drift. Any error in the RREF reflects the same error in the RTD measurement. The REFP0 and REFN0 pins are shown connecting to the RREF resistor as a Kelvin connection to get the best measurement of the reference voltage. This eliminates any series resistance as an error from the reference resistance measurement.