SBAA275A June 2018 – March 2023 ADS1120 , ADS112C04 , ADS112U04 , ADS1147 , ADS1148 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1220 , ADS122C04 , ADS122U04 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS125H02 , ADS1260 , ADS1261 , ADS1262 , ADS1263
An IDAC current source drives the RTD, RREF, and RBIAS. Similar to the two-wire RTD design in Section 2.1, the same current drives both the RTD and RREF, creating a ratiometric measurement so that the ADC output is calculated as a ratio between the RTD resistance and the reference resistance.
However, in a high-side reference application, the measurement requires RBIAS to set the RTD measurement near mid-supply, so that AIN1 and AIN2 are in the range of the PGA. Additionally, using RBIAS increases the DC voltage seen at AIN0, which must be low enough to be within the compliance voltage of the IDAC output.
The measurement circuit requires:
First, identify the range of operation for the RTD. The reference resistance and PGA gain determines the positive full-scale range of the measurement.
Then, choose the reference resistor and IDAC current value. As in the previous circuit topology, choosing the reference resistor and IDAC current balances several design considerations including signal noise, RTD self-heating, setting the input near mid-supply to keep the measurement within the input range of the PGA, and keeping the output voltage of the IDAC within the compliance output voltage. In this high-side reference, the compliance range is more likely to be violated because there is more resistance with the addition of RBIAS.
To verify that the design is within the ADC range of operation, Calculate the voltages for AIN1 and AIN2 and the maximum differential input voltage. Verify that VAIN1 and VAIN2 are within the input range of the PGA given the gain setting and supply voltage. Use the maximum RTD resistance based on the desired temperature measurement. The RBIAS resistance acts as a level shift for the sensor measurement. This level shift raises the DC bias of the analog input signal so that the voltage is within the input range of the PGA. Generally the analog input signal is set near mid-supply for best operation.
Finally, the output voltage of the IDAC source calculated from VAIN0 must be low enough from AVDD to be within the compliance voltage of the IDAC current source. With the addition of RBIAS, the voltage seen across the sum of RREF, RRTD, and RBIAS is significantly higher than the low-side-reference example. When the IDAC output voltage rises too close to AVDD, the IDAC loses compliance and the excitation current is reduced. The output voltage of the IDAC at AIN0 can be calculated from Equation 21.
The reference resistor, RREF must be a precision resistor with high accuracy and low drift. Any error in the RREF reflects the same error in the RTD measurement. The REFP0 and REFN0 pins are shown connecting to the RREF resistor as a Kelvin connection to get the best measurement of the reference voltage. This eliminates any series resistance as an error from the reference resistance measurement.
The lead wire resistance is an error term in the two-wire RTD measurement. The previous calculations neglect the lead resistances, but can be added to the RRTD term.