Input | ADC Input | Digital Output ADS7042 |
---|---|---|
VinDiffMin = –10V | CH_x = –10V | 8000H |
VinDiffMax = +10V | CH_x = +10V | 7FFFH |
AVDD | DVDD | HVDD (VCC) | HVSS(VEE) |
---|---|---|---|
5.0V | 3.3V | +15V | –15V |
Instrumentation amplifiers are optimized for low noise, low offset, low drift, high CMRR and high accuracy but these instrument amplifiers may not be able to drive a precision ADC to settle the signal properly during the acquisition time of ADC. This design will show how a wide bandwidth buffer (OPA827) can be used with an instrumentation amplifier to achieve good settling at higher sampling rate. This INA828 instrumentation amplifier with the buffer drives the ADS8568 SAR ADC to implement data capture for a high voltage fully differential signal which may have a wide common-mode voltage range or a bipolar single-ended signal up to ±10V. A related cookbook circuit shows a simplified approach that does not include the wide bandwidth buffer (Driving High Voltage SAR ADC with an Instrumentation Amplifier), this simplified approach has limited sampling rate as compared to the buffered design in this document. This circuit implementation is applicable to industrial transportation and analog input modules that require Precision Signal-Processing and Data-Conversion.
Specification | Goal | Calculated | Simulated |
---|---|---|---|
Transient Settling Error | < 1/2LSB (< 152µV) | NA | –346nV |
Noise (at ADC Input) | <20µVRMS | 47.2µVRMS | 46µVRMS |
The following graph shows a linear output response for inputs from differential –12.2V to +12.2V. The input range of the ADC is ±10V, so the amplifiers are linear well beyond the required range. Refer to Determining a SAR ADC’s Linear Range when using Instrumentation Amplifiers for detailed theory on this subject. The full-scale range (FSR) of the ADC falls within the linear range of the Instrumentation Amplifier.
The bandwidth for this system is simulated to be 167kHz and the gain is 0dB. The filter between the OPA827 and INA828 limits the bandwidth to about 167kHz.
The OPA827 buffer (22MHz GBW) is used because it is capable of responding to the rapid transients from the charge kickback fromADS8568. The op amp buffer allows the system to achieve the ADS8568 maximum sampling rate of 510kSPS. The following simulation shows settling to a full scale DC input signal with INA828 and OPA827 buffer, and ADS8568.. This type of simulation shows that the sample and hold kickback circuit is properly selected to meet desired ½ of a LSB (152µV). Refer to the Introduction to SAR ADC Front-End Component Selection training video series for detailed theory on this subject.
The section walks through a simplified noise calculation for a rough estimate. We include both the INA828 and OPA827 noise. Note that the RC filter between the instrumentation amplifier and op amp significantly reduces the total noise. The output filter pole is estimated as a second order filter because the OPA827 (22MHz) bandwidth limit and charge bucket filter cutoff frequency (10.2MHz) is close.
Note that calculated and simulated match well- (calculated = 47.2µV, Simulated = 46µV). See TI Precision Labs for detailed theory on amplifier noise calculations, and Calculating Total Noise for ADC Systems for data converter noise.
Device | Key Features | Link | Similar Devices |
---|---|---|---|
ADS8568 | 16-bit, 8 Channel Simultaneous-Sampling, Bipolar-Input SAR ADC | 16-bit, 8-channel, simultaneous-sampling, bipolar-input, SAR analog-to-digital converter (ADC) | Analog-to-digital converters (ADCs) |
INA828 |
Bandwidth 1MHz (G=1), low noise 18nV/rtHz, low offset ±40μV, low offset drift ±0.4μV/°C, low gain drift 0.1ppm/°C (Typical values) |
50-μV Offset, 7-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier | Instrumentation amplifiers |
OPA827 | Gain bandwidth 22MHz, low noise 4nV/rtHz, low offset ±75μV, low offset drift ±0.1μV/°C (Typical values) | Low-noise, high-precision, JFET-input operational amplifier | Operational amplifiers (op amps) |
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