SBAA415 April   2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

 

  1.   Multiple PCM6xx0 Devices With Shared TDM and I2C Bus
    1.     Trademarks
    2. 1 Introduction
    3. 2 Sharing the Control Bus
    4. 3 Sharing the Audio Bus
      1. 3.1 ASI Configuration for Shared TDM
      2. 3.2 ASI Configuration for Daisy Chain TDM
    5. 4 Configuring PurePath Console for Multiple PCM6xx0 EVMs
      1. 4.1 Changing the Default I2C Address of the PCM6xx0 EVM
      2. 4.2 Launching PurePath Console With Multiple Devices
  2.   A PurePath Console I2C Scripts
    1.     A.1 PCM6xx0 I2C Scripts for Shared TDM
    2.     A.2 PCM6xx0 I2C Scripts for Daisy Chain TDM

3 Sharing the Audio Bus

PCM6xx0 devices send the digitized audio data through a Time Division Multiplexed (TDM) audio bus. A set of channel transfers starts at the rising edge of FSYNC with the first slot of data (slot 0), followed by the remaining data slots in increasing order (slot1, slot2, and so forth). A slot contains the converted data from an ADC channel. Each slot transmits a bit on the rising or falling edge of BCLK, starting with the most significant bit first. Figure 3 shows an example for TDM bus operation with eight slots when TX_OFFSET is set to 0. In this figure, FSYNC is the frame sync signal from the host processor, BCLK is the bit clock signal from the host processor, and SDOUT is the bus from the PCM6xx0 devices. PCM6xx0 supports up to 64 slots in the SDOUT output.

tdm-01-adc5140-sbas892.gifFigure 3. TDM Mode Standard Protocol Timing (TX_OFFSET = 0)

For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels times the programmed word length of the output channel data, as shown in Equation 1. For the example shown in Figure 1 with four devices, each with four channels, at a 48-KHz sampling rate and 32-bit word length, BCLK ≥ 4 × 4 × 48 000 × 32 = 24.576 MHz. Since the maximum supported BCLK is 25 MHz, the maximum number of devices is dependent on the number of channels used, sample rate, and word length that maintains a bit clock (BCLK) under 25 MHz.

Equation 1. 25 MHz ≥ bit clock ≥ (# channels/device) × (# devices) × (sample rate) × (word length)

NOTE

For BCLK periods greater than 18.5 MHz (for corresponding sampling rates, see the Supported FSYNC and BCLK Frequencies table of the data sheet), one of the following conditions must be satisfied:

  • The microprocessor must latch DOUT data on same edge clock polarity by adding a one BCLK cycle delay to allow capturing of DOUT transmission.
  • The ADC must add a half cycle delay to DOUT from DOUT transmission at BCLK edge by setting TX_EDGE = 1 in ASI_CFG0 register (Figure 11). This setting adds a 1-bit offset in the data capture to the microprocessor.

Failure to observe these conditions might result in the microprocessor capturing corrupted data from DOUT.

The PCM6xx0 supports two methods of wiring several devices together: Shared TDM or Daisy Chain TDM. The following two sections detail the registers that need to be programmed to configure the PCM6xx0 devices to share the TDM bus in these methods.