SBAA415 April 2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1
The PCM6xx0 devices are controlled through an I2C bus operating in standard mode, fast mode, and fast mode plus. This I2C control bus requires a 7-bit slave address whose two least significant bits are programmable by pulling the ADDR0_SCLK and ADDR1_MISO pins to VSS or IOVDD. By programming different I2C slave addresses through these pins, several PCM6xx0 devices can share a single I2C control bus. Moreover, a programmable broadcast enable feature allows you to temporarily change the I2C slave address to 1001000 for PCM6xx0. This temporary slave address allows for simultaneous broadcasting I2C communication to all PCM6xx0 devices in the system. Table 1 lists the four possible PCM6xx0 device addresses resulting from these pin and broadcast configuration options. In these table entries for ADDR1_MISO and ADDR0_SCLK, the notation '0' refers to pulling the pin to VSS, while notation '1' refers to pulling the pin to IOVDD. The notation 'X' refers to pulling the pin to either VSS or IOVDD.
ADDR1_MISO | ADDR0_SCLK | I2C_BRDCAST_EN Bit Field of SLEEP_CFG Register | I2C Slave Address (BINARY) |
---|---|---|---|
0 | 0 | 0 (default) | 1001 000 |
0 | 1 | 0 (default) | 1001 001 |
1 | 0 | 0 (default) | 1001 010 |
1 | 1 | 0 (default) | 1001 011 |
X | X | 1 | 1001 000 |