3 Edge Sync for I²S and LJF in Controller Mode

In controller mode, the FSYNC edge is synchronous to the rising edge of BCLK. However, standard I²S/LFJ bus format expect the FSYNC edge to be synchronous to the falling edge of BCLK. Figure 3-1 and Figure 3-2 show the timing diagrams supported by PCM6xx0 in I²S and LJF mode, respectively. Note the standard I²S and LJF expect the FSYNC edge one clock cycle later than that produced by the PCM6xx0. To support standard I²S and LJF bus formats, the following sections show configuration options to provide compatibility in controller mode.

Figure 3-1 Default I²S in Controller Mode (TX_Offset = 0) Showing Incompatible FSYNC Edge Sync

Figure 3-2 Default LJF Format in Controller Mode (TX_OFFSET = 0) Showing Incompatible FSYNC Edge Sync