SBAA457 June   2021 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 Compatibility With Non-zero Offset
    2. 3.2 I2S Compatibility With Zero Offset (I2S only)

2.1.1 Auto Clock Configuration With PLL Enabled

The auto clock configuration engine requires four user-provided parameters to generate the proper ASI clocks when the device is configured in controller mode, as shown in Table 2-2.

Table 2-2 Required Input Parameters for Controller Mode Auto Clock Configuration With PLL Enabled
USER-PROVIDED PARAMETERREGISTER
MCLK FrequencyPage 0, MST_CFG0 Register 0x13, Bits 2-0
Sampling Rate (FS) mode (multiple of 48 kHz or 44.1 kHz)Page 0, MST_CFG0 Register 0x13, Bit 3
FS_RATEPage 0, MST_CFG1 Register 0x14, Bits 7-4
FSYNC-to-BCLK RatioPage 0, MST_CFG1 Register 0x14, Bits 3-0