SBAA457 June   2021 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 Compatibility With Non-zero Offset
    2. 3.2 I2S Compatibility With Zero Offset (I2S only)

2.1.2.2 Example

For a 24.576-MHz or 22.579-MHz MCLK, the following I2C script configures the PCM6xx0 as controller mode with GPIO1 as MCLK input for the 48-kHz or 44.1-KHz sampling rate, respectively:

w 90 13 a0 # enable master mode, disable PLL for auto-clock config
w 90 14 48 # FS = 44.1/48k BCLK/fsync ratio = 256 
w 90 16 d8 # MCLK is audio root, use MCLK_ratio_sel, MCLK/Fsync ratio = 512
w 90 21 a0 # configure GPIO1 as MCLK input