SBAA457 June   2021 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 Compatibility With Non-zero Offset
    2. 3.2 I2S Compatibility With Zero Offset (I2S only)

3.2 I2S Compatibility With Zero Offset (I2S only)

PCM6xx0 devices can comply with the I2S bus format with zero offset by modifying the default left justified format to fit the I2S format requirements, as follows:

  • BCLK_POL (Page 0, ASI_CFG0 Register 0x07, Bit 2) = 1
  • TX_EDGE (Page 0, ASI_CFG0 Register 0x07, Bit 1) = 1
  • ASI_FORMAT (Page 0, ASI_CFG0 Register 0x07, Bits 7-6) = 2’b10 (LJF format)
  • FSYNC_POL (Page 0, ASI_CFG0 Register 0x07, Bit 3) = 1

Note that the first three bit fields configure the device in LJF mode with a TX_OFFSET = 1 as in Section 3.1. The fourth bit field flips the polarity of FSYNC to match the I2S protocol.