SBAA483 February   2021 ADS1120 , ADS112C04 , ADS112U04 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1220 , ADS122C04 , ADS122U04 , ADS124S06 , ADS124S08 , ADS125H02 , ADS1260 , ADS1261 , ADS1262 , ADS1263

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Features Used to Detect Wire Breaks in RTD Systems
    1. 2.1 Detecting a Wire Break Using a Continuous VREF Monitor
    2. 2.2 Detecting a Wire Break Using a Periodic VREF Monitor
    3. 2.3 Detecting a Wire Break Using Separate Analog Inputs
  5. 3Wire-Break Detection Methods for Different RTD Configurations
    1. 3.1 Wire-Break Detection Using 2-Wire RTDs
    2. 3.2 Wire-Break Detection Using 3-Wire RTDs
      1. 3.2.1 Wire-Break Detection in a One-IDAC, 3-Wire RTD System
        1. 3.2.1.1 Detecting a Break in Lead 2 in a One-IDAC, 3-Wire RTD System
          1. 3.2.1.1.1 Detecting a Break in Lead 2 in a One-IDAC, 3-Wire RTD System Using a High-Side RREF
        2. 3.2.1.2 Wire-Break Detection Summary for a One-IDAC, 3-Wire RTD System
      2. 3.2.2 Wire-Break Detection in a Two-IDAC, 3-Wire RTD System
        1. 3.2.2.1 Detecting Lead 1 or 2 breaks in a two IDAC, 3-wire RTD system using a low-side RREF
        2. 3.2.2.2 Detecting Lead 1 or 2 Breaks in a Two-IDAC, 3-Wire RTD System Using a High-Side RREF
        3. 3.2.2.3 Wire-Break Detection Summary for a Two-IDAC, 3-Wire RTD System
    3. 3.3 Wire-Break Detection in a 4-Wire RTD System
      1. 3.3.1 Detecting Lead 2 and Lead 3 Breaks in a 4-Wire RTD System Using a Low-Side RREF
      2. 3.3.2 Detecting Lead 2 and Lead 3 Breaks in a 4-Wire RTD System Using a High-Side RREF
      3. 3.3.3 Wire-Break Detection Summary for a 4-Wire RTD System
  6. 4Settling Time Considerations for RTD Wire-Break Detection
  7. 5Summary
  8.   A How Integrated PGA Rail Detection Helps Identify Wire Breaks
  9.   B Pseudo-Code for RTD Wire-Break Detection
    1.     B.1 Pseudo-Code for a 2-Wire RTD System (Low-Side or High-Side RREF)
    2.     B.2 Pseudo-Code for a One-IDAC, 3-Wire RTD System (Low-Side or High-Side RREF)
    3.     B.3 Pseudo-Code for a Two-IDAC, 3-Wire RTD System (Low-Side or High-Side RREF)
    4.     B.4 Pseudo-Code for a 4-Wire RTD System (Low-Side or High-Side RREF)

2.2 Detecting a Wire Break Using a Periodic VREF Monitor

The ADS1220, ADS122C04, and ADS122U04 (as well as their 16-bit counterparts) offer a specific input multiplexer configuration that measures back the external VREF voltage using the internal VREF as the reference. Table 2-1 from the ADS1220 data sheet shows that setting MUX[3:0] = 1100b measures (VREFPx – VREFNx) / 4. In the event of a wire break where no current flows through RREF, this measurement is approximately 0 V, indicating a fault.

Table 2-1 Enabling the ADS1220 Periodic VREF Monitor Using the MUX[3:0] Bits
Bit Field Type Reset Description
7-4 MUX[3:0] R/W 0h

Input multiplexer configuration

These bits configure the input multiplexer. For settings where AINN = AVSS, the PGA must be disabled (PGA_BYPASS = 1) and only gains 1, 2, and 4 can be used.

0000: AINP = AIN0, AINN = AIN1 (default)

0001: AINP = AIN0, AINN = AIN2

0010: AINP = AIN0, AINN = AIN3

0011: AINP = AIN1, AINN = AIN2

0100: AINP = AIN1, AINN = AIN3

0101: AINP = AIN2, AINN = AIN3

0110: AINP = AIN1, AINN = AIN0

0111: AINP = AIN3, AINN = AIN2

1000: AINP = AIN0, AINN = AVSS

1001: AINP = AIN1, AINN = AVSS

1010: AINP = AIN2, AINN = AVSS

1011: AINP = AIN3, AINN = AVSS

1100: (V(REFPx) – V(REFNx)) / 4 monitor (PGA bypassed)

1101: (AVDD – AVSS) / 4 monitor (PGA bypassed)

1110: AINP and AINN shorted to (AVDD + AVSS) / 2

1111: Reserved

The challenge with this approach is that the VREF voltage cannot be monitored continuously. Instead, halt RTD measurements and switch over to the monitoring channel, increasing system latency and complexity compared to using an ADC with a continuous VREF monitor. Choose how often to interleave diagnostic measurements by balancing increased latency with the required system response time to a fault condition.