SBAA487 January   2021 ADS8664 , ADS8668 , ADS8674 , ADS8678 , ADS8684 , ADS8684A , ADS8686S , ADS8688 , ADS8688A , ADS8694 , ADS8698

 

  1.   Trademarks
  2. 1Introduction
  3. 2Phase Delay and Non-Simultaneous Sampling
  4. 3Averaging with Sequencer and Burst Sequencer mode
    1. 3.1 Averaging with Sequencer
    2. 3.2 Averaging with Burst Sequencer
  5. 4Verification and Measured Result
    1. 4.1 Phase Delay Measurement
      1. 4.1.1 Measured Phase Delay without Averaging – 50Hz Sinusoidal Fundamental Signal
      2. 4.1.2 Measured Phase Delay with Averaging – 50Hz sinusoidal fundamental signal
      3. 4.1.3 Comparison
    2. 4.2 AC Performance
  6. 5Summary
  7. 6References

3.2 Averaging with Burst Sequencer

The Sequencer mode is very flexible to select the channels in the specific order, while the ADS8686S also offers an additional Burst mode; the Burst feature is applicable only when the sequencer mode is enabled.

When the Burst mode is enabled, only one CONVST pulse can initiate the conversions for all input channels configured in the sequencer instead of more CONVST pulses required in the Sequencer only mode. By using the Burst Sequencer mode, the sample averaging method can significantly save the resource on the host controller or processor.

The Burst Sequencer can operate at either hardware mode or software mode. In hardware mode, the Burst Sequencer mode is enabled by setting the BURST and SEQEN pins on ADS8686S to high. The CHSEL[2:0] are logic pins to select input channels or program the hardware mode sequencer, the logic levels of CHSEL[2:0] pins are launched when the /RESET pin is released these levels determine the channel sequence selected for the conversion and averaging in the Burst Sequencer mode. Refer to the ADS8686S16-Channel, 16-Bit, 1-MSPS, Dual, Simultaneous Sampling ADC with Integrated Analog Front-End Hardware Mode Burst Sequencer section 7.4.2.6.1 data sheet for the details.

The timing for the Burst Sequencer in hardware mode is shown in Figure 3-2, and only one CONVST pulse is required for the data conversion on all input channels.

GUID-20210106-CA0I-CTQT-TZ7G-G1KF7LR7R12Q-low.gif Figure 3-2 Timing for Burst Sequencer, Hardware Mode

In software mode, setting the BURST bit in the Configuration Register to 1 can enable the Burst function. Also, setting the SEQEN bit in the Configuration Register to 1 can enable the Sequencer function. The ADS8686S offers a 32-stack, configurable sequencer. The sequencer stack registers are used to select the channels for data conversion in a certain order according to the channel sequence introduced in the section 3.1 for sample averaging. Refer to the ADS8686S16-Channel, 16-Bit, 1-MSPS, Dual, Simultaneous Sampling ADC with Integrated Analog Front-End section 7.4.2.6.2 data sheet for further details about Software Mode Burst Sequencer.