SBAA583 july 2023 PCM1820 , PCM1820-Q1 , PCM1821 , PCM1821-Q1 , PCM1822 , PCM1822-Q1 , PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120
A low noise performance as well as good common mode handling can be obtained by using the setup below.
For the TLV320ADC6120 device, the SNR in Table 3-3 is achieved.
SNR( DRE ON) dB | SNR(DRE OFF) dB |
---|---|
112 | 108 |
For a DC-coupled input, the DRE scheme can be used with limited DRE_MAXGAIN depending on the DC differential input common-mode offset.